Siemens S5 STL: Fixing Flag Bit RLO Reset with Missing Coil

Problem: Flag Bit F244.5 Resets Between STL Segments on the S5-95U

A long-running STEP 5 program on an Siemens S5-95U (CPU 95U, order number 6ES5 095-8ME01 and related variants in the 6ES5 095-8xxxx family) contains a function block that monitors a manual command path and a normal-operation status. The programmer adds new logic in segments 17, 18, and 19. During online monitoring with the PG (PG 685, PG 710, PG 740, or PG 760 with STEP 5 V7.x), the coil assignment in segment 17 lights the flag F 244.5, but as soon as the CPU sweeps into segment 19 the same bit reads as 0 and the RLO is also 0. The programmer reasonably expects a flag written by = (coil assignment) to remain 1 until something else forces it low.

This article documents the precise cause: in STEP 5 STL (Statement List, also called AWL in German documentation), the L (Load) and T (Transfer) instructions operate exclusively on the accumulators and never gate on the current Result of Logic Operation (RLO). When segment 18 evaluates to RLO = 0 because no terminating coil is present, that RLO = 0 becomes the new RLO that segment 19 inherits. Any A (AND) instruction at the top of segment 19 then AND-combines the inherited RLO with the flag operand, producing 0 and erasing the user's mental model of how the bit should behave.

Symptom Summary: Online Monitor Shows Bit Cleared

The defect shows three reproducible symptoms when monitored on the PG:

1. Coil status flicker. F244.5 in segment 17 reads 1 in the Aktualwert (current value) column immediately after the = instruction fires.
2. Inherited RLO = 0. As soon as segment 18 finishes (with no terminating coil), the RLO entering segment 19 is forced to 0 by the AND combination of F 242.1 and F 242.6.
3. Downstream logic collapses. The limit-check in segment 19 (<F with DW 9 as default) never executes the load/transfer pair because RLO is 0, even though F 244.5 still holds 1 in memory.

The flag is fine. The program structure is the problem.

Root Cause: STL Load and Transfer Do Not Gate on RLO

The STEP 5 instruction set, as documented in the original Siemens STEP 5 Reference Manual (order number 6ES5 998-0PR21, also distributed in English as EWA 4NEB 812 6120-02), splits instructions into two independent categories based on whether they consume the RLO:

The consequence is brutal and unambiguous: writing L KF +1000; T DW 41; T DW 42; in segment 18 performs the load and transfers unconditionally, regardless of whether segment 18's first-scan logic is true or false. Because nothing terminates segment 18 with a coil (=, S, R, JC), the RLO at the end of segment 18 is the result of the very last binary instruction - in this case the AND of F 242.1 and F 242.6. If either operand is 0 at scan time, the segment terminates with RLO = 0.

Segment 19 then begins with A F 244.5. The A instruction performs a logical AND of the previous RLO (= 0, carried over from segment 18) with the operand F 244.5 (= 1, the actual stored value). The result is 0, and that 0 is the RLO now displayed in the monitor for segment 19. The PG faithfully reports the current RLO, not the flag's stored bit.

Anatomy of the Faulty Program (DB162 Context)

The block under repair opens DB 162 earlier (likely with C DB 162 or the implicit A DB 162 in a call environment). All references to DW 41, DW 42, DW 5, and DW 9 therefore resolve inside the 256-word data block image. The flag references (F 242.1, F 242.5, F 242.6, F 244.5) live in the internal flag area of the S5-95U, which on this CPU is 2048 flags (F 0.0 through F 255.7), with the upper 256 flags (F 200.0 to F 255.7) typically used for retentive or system-flag purposes.

The three segments under review:

; Segment 17 - defines "Normal operation" latching flag
A   F 242.5   ; Manual command ON  (button input)
A   F 242.1   ; Manual status      (mode bit)
=   F 244.5   ; Normal operation (PROBLEM: this works, but doesn't survive scan 18)

; Segment 18 - supposed to write 100% setpoint when Manual-OFF is pressed
A   F 242.1   ; Manual status
A   F 242.6   ; Manual command OFF
L   KF +1000  ; 100% engineering units
T   DW 41     ; Set FAD position (FRESH AIR DAMPER)
T   DW 42     ; Set RAD position (RETURN AIR DAMPER)
; *** MISSING TERMINATING COIL ***

; Segment 19 - clamp damper setpoint to damper minimum
A   F 244.5   ; Manual command ON (looks 0 here because RLO was inherited from seg 18)
L   DW 5      ; FAD setpoint
L   DW 9      ; Damper Min position
<F
L   DW 9
T   DW 41     ; Set FAD position

The single structural defect is the absence of a terminating instruction in segment 18. Without it, the RLO produced by A F 242.1; A F 242.6 propagates as the starting RLO of segment 19. The L/T pairs in both segments execute regardless, but the RLO display in the monitor makes the program look wrong.

How the S5 CPU Evaluates RLO Step by Step

The S5-95U scan model for a single FB/OB segment sequence works as follows:

1. Segment entry. The RLO at the start of every segment is the value left in the RLO bit of the Statuswort (status word) by the previous segment - unless the segment begins with a first scan bit (A I x.y, A F x.y, etc.) that forces a fresh AND operation.
2. Binary instruction evaluation. A performs RLO = RLO AND operand. The operand is fetched from the process image (for inputs) or flag area (for flags), but the RLO is the boolean state of the previous segment at that exact scan cycle.
3. Accumulator operations. L loads the operand into ACCU 1, shifting ACCU 1 into ACCU 2. T copies ACCU 1 to the destination. Neither touches the RLO.
4. Terminating instruction. A coil (=), set (S), reset (R), or jump (JC, JCN) reads the current RLO and writes it to the operand or PC, then clears the RLO to start the next segment fresh. This is the only safe way to terminate a segment.
5. Unterminated segments. If a segment ends without one of the above, the last binary instruction's AND result is left in the RLO. That result is what the next segment inherits.

The Missing Coil: Why Segment 18 Silently Drops F244.5

Segment 18's logic evaluates as follows when F 242.1 = 1 and F 242.6 = 0 (Manual status = ON but Manual-OFF button not pressed):

1. RLO inherits from segment 17. Segment 17 ended with = F 244.5, which wrote 1 to F244.5 and cleared the RLO to 0 for the next segment. (This is what coils do - they terminate the scan chain.)
2. A F 242.1 evaluates: RLO_new = 0 AND 1 = 0.
3. A F 242.6 evaluates: RLO_new = 0 AND 0 = 0.
4. L KF +1000: RLO untouched (still 0).
5. T DW 41: transfer occurs, RLO still 0.
6. T DW 42: transfer occurs, RLO still 0.
7. Segment 18 ends with RLO = 0 because no coil was written.
8. Segment 19 begins: A F 244.5 performs RLO_new = 0 AND 1 = 0.
9. Monitor displays RLO = 0 for segment 19. The flag is unchanged in memory, but the RLO is misleading.

The transfers in segment 18 always execute, which is a second hidden bug: every scan writes 100% to DW 41 and DW 42 regardless of whether Manual-OFF was pressed. In an HVAC damper loop, that means the FAD and RAD setpoints are slammed to 100% every cycle, and the only thing keeping them at the right value is the subsequent limit clamp in segment 19 - which, as we have just established, is itself broken because of the inherited RLO.

Fix 1: Conditional Jump (JC) Pattern

The classic STEP 5 idiom for conditional word operations uses JC (Jump if RLO = 1) to gate the L/T pair. The corrected segment 18 looks like this:

; Segment 18 - corrected: only set 100% when Manual-OFF is active
A   F 242.1   ; Manual status
A   F 242.6   ; Manual command OFF
JC  =SEG18     ; jump to M001 if RLO = 1
JU  =SEG18B    ; otherwise jump to end
SEG18:
L   KF +1000   ; 100% engineering units
T   DW 41      ; Set FAD position
T   DW 42      ; Set RAD position
SEG18B:
NOP 0

The JC =SEG18 instruction terminates segment 18's RLO. If the jump is taken, the next segment begins with a fresh RLO = 0 (because JC consumes and resets RLO). If the jump is not taken, JU =SEG18B (Jump Unconditional) forces termination and the program also starts fresh. The 100% write is now gated to scan cycles where both F 242.1 and F 242.6 are 1.

Symbolic labels (=SEG18) are resolved by the STEP 5 compiler from the symbol table (entered with Symbol Editor or the SY1 / SY2 files). You can also use absolute jump targets such as JC M001 if the label table is not active in this block.

Fix 2: Conditional Assignment Using AND Mask

For very compact code where you cannot add jump labels, mask the L/T pair with an AN / A pre-condition:

; Segment 18 - alternative: use a coil to terminate RLO, then guard L/T
A   F 242.1
A   F 242.6
S   F 245.0    ; one-shot flag for "Manual-OFF active this scan"

A   F 245.0
L   KF +1000
T   DW 41
T   DW 42
R   F 245.0    ; clear flag for next scan

This version still does an unconditional transfer (L/T never gate RLO on S5), but the writing of 100% is now scoped to scans where F 245.0 is 1. The S and R instructions terminate their respective sub-logic chains and reset the RLO cleanly.

Fix 3: Restructuring with S and R Instead of =

For damper control where Manual-OFF is an edge event (button press rather than level), use edge detection with FP (FlankenPositiv / positive edge):

; Segment 18 - edge-triggered manual OFF
A   F 242.1
A   F 242.6
FP  F 245.1    ; edge flag, F245.1 = 1 for one scan after rising edge

A   F 245.1
JC  =DO_WRITE

JU  =END18
DO_WRITE:
L   KF +1000
T   DW 41
T   DW 42
END18:
NOP 0

The FP instruction sets its associated flag for exactly one OB1 cycle after a 0 -> 1 transition on RLO. Combined with JC, this gives you a clean one-shot without any timer (T 0-T 31 on S5-95U are 100 ms / 1 s / 10 s depending on TK flag).

Modern Parallels: RLO Behavior in S7-1500 STL (TIA Portal)

STEP 7 in TIA Portal preserves the same RLO semantics, so engineers porting S5 code to S7-1500 will hit the identical class of bug. Siemens now documents the explicit CLR instruction as a way to explicitly reset RLO to 0, which is useful when you want a guaranteed clean segment boundary. See the official TIA Portal documentation: CLR: Reset RLO to 0 (S7-1500) in the TIA Portal Help V20.

The companion instruction RESET_BF (Reset Bit Field) is the modern equivalent for clearing a contiguous range of bits in a flag/DI/DB area, useful when migrating the manual-mode reset logic: RESET_BF: Reset bit field (S7-1200, S7-1500) in Siemens Industry Online Support (entry ID 109747174).

On S7-1500 you would write the equivalent of segment 18 as:

; S7-1500 STL equivalent (TIA Portal V20)
A   "ManualStatus"    ; %M10.1
A   "ManualOFFCmd"    ; %M10.6
JC  L001              ; terminate RLO if condition true
JU  L002              ; otherwise skip
L001:
L   1000
T   "DB162".FAD_SP    ; %DB162.DBW40
T   "DB162".RAD_SP    ; %DB162.DBW42
L002:
CLR                   ; explicit RLO reset (optional on S7-1500)

The structural pattern is identical to S5 STL. The only differences are the operand prefixes (%M, %DB162) and the availability of CLR as an explicit instruction.

Verification: Online Monitoring and Test Sequence

After applying Fix 1 (JC pattern) and uploading to the CPU, run this verification sequence on the PG with STEP 5 V7.23 or later and the online monitor connected via the COM port / MPI / TTY interface:

1. Force Manual status. Set F 242.1 = 1 using PG Force / Status Variable. Confirm F 244.5 goes to 1 within one OB1 cycle.
2. Pulse Manual-OFF. Toggle F 242.6 = 1 for exactly one scan (use a one-shot timer or edge from a real pushbutton). Confirm DW 41 and DW 42 read 1000 in the data view of DB 162.
3. Monitor segment 19. Open the FB in online mode. With F 244.5 = 1, confirm that the RLO at the top of segment 19 reads 0 initially and then transitions to 1 after the first A F 244.5 is evaluated (because the JC in segment 18 cleared RLO). The flag itself still reads 1 in the operand column.
4. Functional check. Drive DW 5 below DW 9 and verify the limiter clamps DW 41 to DW 9. The L/T in segment 19 will now actually fire on every scan where F244.5 = 1.
5. Watchdog check. Confirm OB1 cycle time remains under 100 ms. JC and JU add microseconds, not milliseconds, on the S5-95U.

Common S5-95U STL Pitfalls

Beyond the missing-coil bug, the S5-95U STL environment has several recurring traps that produce similar confusing symptoms:

Best Practices for S5-95U STL Programming

When maintaining or writing new STL on the S5-95U, apply these rules consistently:

• Always terminate a segment. Every segment that contains a binary instruction must end with =, S, R, JC, JCN, JU, JCB, or JNB. This guarantees an RLO reset for the next segment.
• Never rely on L/T to gate behavior. Use JC or a flag to gate word operations explicitly.
• Use FP / FN for edge detection instead of polling raw inputs in every segment - this reduces scan load and prevents RLO confusion.
• Name flags in the symbol table. F 242.5 is meaningless; F 242.5 = "ManualCmdON" is searchable.
• Document the segment header. Add a *** comment line at the top of each segment explaining the purpose. STEP 5 ignores comment lines starting with ;, and the PG displays them in online mode.
• Compile and download after every change. The S5-95U does not hot-reload code; use File > Download to AG in STEP 5 and confirm the CPU is in STOP or RUN-P mode.
• Back up the EPROM/EEPROM. For permanent fixes, burn the corrected FB to a 27C256 EPROM (or use the on-board EEPROM on later 95U variants) and label the chip with the program date.

The original defect in this case was a one-character oversight (a missing terminating coil), but its effect propagated through three segments and hid the real cause for several online-monitoring sessions. Understanding that L and T ignore RLO, and that unterminated segments leak their RLO into the next segment, is the single most important mental model for STEP 5 STL programmers - and it transfers directly to S7-1500 STL in TIA Portal V20.