S7-1200 Analog Input Resolution 10/12/13/16-bit ADC Configuration

Overview: S7-1200 Analog Input Resolution Architecture

On the SIMATIC S7-1200, the analog-to-digital conversion resolution is determined by the hardware module you select, not by software configuration. The S7-1200 family exposes three distinct resolution tiers:

• CPU onboard analog inputs — fixed 10-bit resolution (1,024 distinct codes, 0–27,648 nominal scaled range)
• Signal Boards (SB) — plug into the CPU front, single channel, 12-bit
• Signal Modules (SM) — connect on the right side of the CPU, 4 or 8 channels, 13-bit or 16-bit

There is no firmware register, configuration switch, or TIA Portal property that increases the resolution beyond the hardware limit. The only software-accessible controls are (1) integration time / noise rejection, which trades conversion time for effective resolution, and (2) post-conversion bit reduction through shift-right (SHR) or bit-mask (WAND) operations. This article documents the exact parts, scaling rules, configuration steps, and reduction techniques.

CPU Onboard Analog Inputs: 10-bit Baseline

Every S7-1200 CPU ships with two integrated analog inputs on the bottom terminal block, labelled AI0 and AI1 on the CPU body. The converter used in the CPU silicon provides 10 bits of effective resolution across a fixed 0–10 V measurement range. Because the CPU cannot be retrofitted, this 10-bit limit is absolute for the onboard channels.

For a 0–10 V signal, a single code step equals 10 V / 1024 ≈ 9.77 mV at the converter. When scaled to the engineering units 0–100 % using the Siemens nom 0–27,648 rule, the smallest representable increment is 100 / 1024 ≈ 0.0977 % per LSB. This is the figure the application sees.

S7-1200 Signal Boards (SB): 12-bit Single Channel

Signal Boards (SB) are small daughter cards that plug into the front of the CPU. They are mechanically keyed for the voltage / current / RTD / TC variant. The standard analog-input signal board is:

• 6ES7231-4HA30-0XB0 — SB 1221, AI 1 × 12 bit, single-ended, 0–10 V or 0–20 mA (selected by terminal wiring)

The SB occupies the front slot and does not consume any slot number in the S7-1200 signal-module chain. Up to one SB per CPU is allowed. SB 1221 is the right choice when only a single high-resolution channel is needed and rack space is at a premium.

S7-1200 Signal Modules (SM): 13-bit to 16-bit Options

Signal Modules (SM) attach to the right side of the CPU and are address-mapped as standard I/O. Three AI resolutions are catalogued for the 4-channel SM 1231 family:

The 16-bit SM (6ES7231-5ND30-0XB0) is the workhorse for instrumentation: it accepts ±10 V, 0–10 V, 0–20 mA, 4–20 mA, plus the standard thermocouple and RTD ranges when used with the TC / RTD variants. The 13-bit SM (6ES7231-4HD30-0XB0) is adequate for valve position, level, and flow applications where the input signal has not been pre-amplified to 16-bit cleanliness.

All SM 1231 AI modules are isolated channel-to-channel and channel-to-backplane, with 24 V DC field-side power. The integration-time selection in TIA Portal controls the trade-off between conversion speed and effective noise rejection.

Standard Analog Value Range: 0 to 27,648 and the 10 % Overrange

Regardless of hardware resolution, the S7-1200 scales every analog channel to the Siemens nominal range used across the SIMATIC family (S7-200, S7-300, S7-400, S7-1200, S7-1500):

The LSB of a 10-bit converter is therefore 27,648 / 1,024 ≈ 27 codes at the integer level, or 10 V / 1,024 ≈ 9.77 mV at the input level. The LSB of a 16-bit converter is 27,648 / 65,536 ≈ 0.42 codes (sub-LSB at the integer level) or 10 V / 65,536 ≈ 0.1525 mV at the input level. The integer span stays the same — only the bit count between codes changes.

Integration Time, Noise Rejection, and Effective Resolution

The hardware resolution is the converter capability. The effective resolution the application sees is lower, and is governed by:

1. Input noise (thermal, EMI, ground loop)
2. Integration time selected in TIA Portal
3. Channel-to-channel settling on the multiplexer

In the device configuration, expand Analog inputs → AI configuration → Channels. Each channel exposes a Integration time drop-down with three pre-sets:

Selecting 10 ms (the most-used pre-set) both filters mains interference and increases the effective number of bits (ENOB) the SM can deliver. With a clean 16-bit SM 1231, an integration time of 10 ms typically yields ENOB in the 14–15-bit range. Selecting 2.5 ms recovers speed but degrades ENOB to ~12 bits because the Sinc3 filter inside the ΔΣ modulator is notched out.

For most flow, level, and temperature applications, the 10 ms default is correct. Use 2.5 ms only for dynamic pressure, vibration, or torque applications where 400 Hz update is needed.

Reducing Effective Resolution: SHR (Shift Right) Method

If the application does not need the full 10-bit (or 12/13/16-bit) converter, you can deliberately truncate the low-order bits in user code. The simplest tool is the SHR (Shift Right) instruction in STEP 7 (TIA Portal). SHR divides the input by 2ⁿ and discards the remainder.

To turn a 10-bit reading into an 8-bit reading:

// In a function block (SCL / ST)
// Latch raw AI value
iRawINT := "AI_BFW".VALUE;       // 16-bit INT from %IW

// Shift right 2 bits to drop the bottom 2 LSBs
iReduced := SHR(IN := iRawINT, N := 2);

In LAD (ladder logic), the equivalent contact-network implementation is:

|     iRawINT    SHR     iReduced |
|---[ MOVE ]----[IN N:2 ]-------( )---|

For a CPU with 10-bit resolution (0–27,648 range) the SHR parameter values map to:

This is the same technique the S7-1200 firmware uses internally when configuring a higher-resolution SM into a legacy code base that expects 10-bit integer scaling. The advantage over the masking method (below) is that the LSB weight scales correctly without any human arithmetic.

Reducing Effective Resolution: Bit Mask (WAND) Method

If you want explicit control over which bits remain — e.g. keep only the top 6 bits to suppress jitter, but skip a known noisy bit — use the WAND_W (Word AND) instruction with a bit-mask constant. This is exactly the approach suggested in the canonical Siemens engineering answer cited above.

Example: keep the top 6 bits of a 16-bit reading by masking the bottom 10 bits to zero:

// Mask = 1111 1100 0000 0000  (FC00 hex)
wMasked := WAND_W(IN1 := "AI_BFW".VALUE,  // 16-bit word from %IW
                  IN2 := 16#FC00);

The resulting word contains 6 valid bits, mapping the original 0–27,648 signal onto 0–864 (6 bits × 27 = 162 codes effective, but the integer carries full bit pattern for clarity). Useful masks:

WAND is preferable to SHR when the masking bit pattern is non-contiguous (e.g. 1111 0000 0011 1100 to drop two specific noisy bits in the middle of the word). Otherwise, SHR is faster to write and harder to make a typo in.

Why You Cannot Increase Hardware Resolution

This is the most-asked variant of the question. The fundamental limits are:

1. Converter bit count is set by the ΔΣ modulator in the SM / SB. The modulator is fabricated onto the silicon die; it cannot be reconfigured in firmware.
2. Reference voltage stability defines the absolute LSB. A 10-bit reference settles to 1 mV; a 16-bit reference settles to 76 µV. The reference is a hardware block.
3. Input amplifier noise is also a hardware constant. The CPU's onboard front-end amp has a noise floor that masks anything below 10 bits; the 16-bit SM 1231's instrumentation amp is two orders of magnitude quieter.

Software-side tricks such as oversampling and averaging can increase the apparent resolution by trading speed for noise. With a 16-bit SM and N=16-sample rolling average at 400 Hz, the effective ENOB climbs by ~2 bits (because random noise averages as √N). The trade-off is that your channel update is now 16 / 400 = 40 ms, which is unacceptable for closed-loop control but fine for tank-level averaging.

Analog Devices’ Mixed-Signal and DSP IC product family provides the converter ICs used inside many SIMATIC modules. For an independent refresher on how ΔΣ ADCs trade sample rate for ENOB, see the analog signal overview and the linked Nyquist / oversampling articles.

TIA Portal Configuration Procedure

To configure analog inputs in the TIA Portal (V16 / V17 / V18 / V19), follow this sequence:

1. Open the project and double-click the Device & Networks view.
2. Select the CPU in the rack view. The right pane switches to Properties → General.
3. Expand Analog inputs → AI configuration → AI0 (and AI1, AI2, AI3… as required).
4. Set Measurement type (Voltage / Current / RTD / TC).
5. Set Output range (e.g. 0–10 V, 4–20 mA, ±10 V).
6. Set Integration time (10 ms recommended for 50/60 Hz mains).
7. If using an SM, ensure the SM is dragged from the hardware catalog into the rack slot. TIA Portal auto-allocates input addresses (e.g. %IW64 for SM 1231 AI 4 × 16 bit slot 0).
8. Compile and download the hardware configuration.

The raw AI word is now available at the I/O symbol (e.g. "AI_BFW") as a 16-bit INT. Apply NORM_X / SCALE_X with the input range 0–27,648 to convert to engineering units.

Verification: Reading and Scaling in STEP 7

Confirm resolution in a watch table or HMI tag:

1. Force the analog input to 0.00 V (short input to COM). Read %IW → expect a value near 0.
2. Force the analog input to 10.00 V (precision calibrator). Read %IW → expect 27,648 ± integration-time noise.
3. Force 5.00 V (half-scale). Expect 13,824 ± ~±5 codes (10-bit) or ~±1 code (16-bit).

If the watch-table value is sticky at one integer when you sweep the calibrator, the SM is in “Overflow” diagnostic — check the device diagnostics buffer in TIA Portal under Online & diagnostics → Diagnostic buffer. If the value jitters by more than ±20 codes on a clean signal, integration time is set to 2.5 ms / 400 Hz; switch to 10 ms.

Resolution Selection Decision Matrix

Troubleshooting Matrix

Frequently Asked Questions