S7-1200 CPU 1214C Mode Selector, Scan Cycle, and Memory Reference

Overview

The SIMATIC S7-1200 CPU 1214C is a compact controller in the Siemens S7-1200 family. Unlike the older S7-300 and S7-400, and unlike the S7-1500, the CPU 1214C ships without a physical mode selector on the front of the module. There is no RUN/STOP/MRES toggle to turn by hand. Every change between RUN, STOP, and reset-to-factory must be triggered either from the engineering station (PG/PC running TIA Portal) or from a HMI / OPC UA / Modbus peer that holds the appropriate permission, or from the CPU's Web Server.

This reference consolidates the three engineering questions that arise from the missing mode selector:

1. How do operators start or stop the CPU when no PG and no TIA Portal are available?
2. How does scan order affect a network that sets and resets the same tag in a single scan?
3. When should M-bit scratch memory be preferred over direct Q-bit writes, and how is L (local) memory addressed in TIA Portal?

All S7-1200 firmware from V1.0 through V4.7 (latest publicly released) is covered; specific restrictions apply to TIA Portal V11 SP2 builds.

CPU 1214C Hardware Layout and the Missing Mode Selector

The CPU 1214C comes in two DC/DC/DC and DC/DC/RLY variants (Siemens catalog 6ES7214-1AG40-0XB0 for DC/DC/DC and 6ES7214-1BG40-0XB0 for DC/DC/RLY). Front-panel elements are:

Compare this to the S7-1500 CPU 1515-2 PN, whose mode selector sits to the right of the display and exposes three positions with mechanical feedback (see S7-1500 Mode Selector):

• RUN – CPU executes the user program; configuration changes are blocked.
• STOP – CPU does not execute the user program; outputs go to the configured substitute or keep-last value.
• MRES – momentary position to perform a memory reset / retain reset.

The S7-1200 collapses that mechanism into software control. Three factors justify the design choice:

1. Cabinet depth in compact machines is often below 250 mm; the toggle would force a wider housing.
2. Unauthorized physical access to the cabinet must not allow an operator to pull the system out of RUN.
3. Remote service is the primary restart path for modern remote-pump and HVAC applications, so the controller is HTTP/Modbus/OPC UA reachable anyway.

Starting and Stopping the CPU Without a PG

Operators routinely need to stop a machine for maintenance without opening TIA Portal. The four accepted procedures are listed below in order of recommendation.

Procedure 1 - TIA Portal online command (engineering station only)

1. In the project tree, mark the CPU 1214C node.
2. Open the menu Online.
3. Select Start CPU or Stop CPU. The dialogue confirms access level and operator name.

This is the official method documented in Siemens Support entry 88781826. The RUN/STOP LED on the front of the CPU toggles within 100-300 ms after the command.

Procedure 2 - HMI button wired to the PLC tags

On any SIMATIC HMI (Basic Panel KTP400 Comfort, or a WinCC Runtime Advanced PC) create a button and link its Pressed event to a tag that drives the following program.

// Bit in an FB "HMI_Control" static area
#bStart := bHmiStart;
#bStop  := bHmiStop;

// Drive the CPU mode through the system clock bits
IF #bStart THEN
    "SetCPU_To_RUN"();   // FB using SFB 23/24 or WRREC to PASS opcode
END_IF;
IF #bStop THEN
    "SetCPU_To_STOP"();
END_IF;

On the S7-1200 the cleanest implementation uses the system function block WRREC to write record 0x0010 (operating mode) of the device. Wrap it in a vendor-supplied FB or the Open User Communication block from the S7-1200 Motion Control library. Implementation note: only a client with the Operating Mode access right can move the controller; the standard project defaults grant this to all HMI devices on the same subnet unless the security configuration is hardened in TIA Portal > Project tree > CPU > Properties > Protection.

Procedure 3 - Web Server page

1. Enable the Web Server under CPU Properties > Web Server and assign an administrator name/password.
2. Create a user-defined web page that calls a function block ("Web_Run_Stop") which writes record 0x0010.
3. Operators reach the panel via http://<CPU-IP>/ using any browser, sign in, and toggle RUN/STOP.

Procedure 4 - Discrete wiring with password-protected authority

For machines without an HMI a digital input configured with "CPU stop from digital input" provides a hardware line to shut down. Enable the option under CPU Properties > System > CPU stop from digital input; choose the DI; define an edge ("Falling") and a hard delay. A momentary dry contact across the configured pair of terminals drops the CPU to STOP. This is field maintenance, not an operator control, so reserve it for E-Stops' safety chain or for panel cut-out door switches.

Scan Cycle and Order of Solve in the S7-1200

The S7-1200 executes the user program in the cyclic organization blocks OB1 (priority class 1) and any additional cyclic OBs added by the user or by libraries (OB 200, OB 201, ...). Each cycle follows the same four phases:

1. Output of the process-image partition onto the physical outputs.
2. Read the inputs into the process-image partition.
3. Execute the user program from the first network of OB1 through the last network of the lowest-priority OB still scheduled.
4. Run the self-test, refresh the communication stack, copy image back to outputs.

Within step 3, the CPU solves networks strictly from top-left network to bottom-right network in the listed network order. There is no pre-processing, no parallel evaluation, no compiler reordering - the literal sequence of networks is the scan order. The principle is identical to traditional relay wiring: the left side of the rung is solved before the right side, and the top rung is solved before the rung below it.

Order-of-solve pitfall - set/reset in the same scan

Consider this ladder pattern in a single network:

|  Tag1    Tag2              Tag3 (SET coil)  |
|  --||--+--||--(S) Tag3                              |
|                  Tag3 (RESET coil)                  |
|                  --||/ (R) Tag3--                   |

If Tag1, Tag2 and the normally-closed contact of Tag3 are all TRUE during the same scan, the network writes Tag3 = 1 with the set coil before it evaluates the reset line. In ladder logic the entire rung is solved left-to-right, so the reset at the same priority level in the same network runs after the set, and Tag3 ends the scan as 0.

This is the classic "order of solve" gotcha. Three rules keep the program deterministic:

1. Never drive a coil from two parallel branches in the same network if both branches contain logic that could go TRUE simultaneously.
2. Use the explicit SR/RS flip-flop instanced in the Instructions > Bit logic catalog; its internal priority is fixed (SR: reset wins; RS: set wins) and identical on every firmware.
3. Split the set and reset across two networks of known order (set above, reset below) so the reviewer's mental model matches the CPU's execution.

Example - scan-safe toggle

The textbook edge-triggered T flip-flop with two networks:

NETWORK 1   // Detect rising edge of Tag_in
      "Tag_in"  P
      FP_Trig    M0.0
NETWORK 2   // Toggle on the rising edge
      M0.0         "Tag_latch"   CN
      --||---------(CN)--------------

The rising-edge bit M0.0 is set by FP_Trig during scan N and cleared by the system at the start of scan N+1 (OB1 PRIOFLAGS in IEC 61131-3). The toggle contact <CN> runs once per cycle because M0.0 is single-shot. Result: the flip-flop changes state exactly once per rising edge of Tag_in - regardless of how long the input remains TRUE.

M Memory vs Q Memory - When to Use Each

M memory (Merker) is the workhorse scratchpad of the S7-1200. The default address range is MB0 ... MB4095 (4 KB) on CPU 1214C, 1215C and 1217C, shared by all OBs. M bits are not wired to anything physical; they exist only in the CPU's load memory and process image.

The canonical pattern is to compute generic logic with M bits and DB tags, then write the final Q bit in a single network that maps "Machine.Heat_On" to Q0.0. This decouples engineering: the algorithm can be unit-tested, transferred, and reused without rewiring. Forcing a Q bit from TIA Portal temporarily bypasses the logic; forcing an M bit temporarily modifies the algorithm - the latter is usually what is desired when troubleshooting.

Allocation recommendations

• Reserve MW0 ... MW99 for engineering, simulator, and test routines - never used by application code.
• Reserve MW100 ... MW199 for hand-shake flags between cyclic OBs (cycle handshake, edge latch).
• Use DB tags for application state. Naming convention stat.<area>.<name> or data.<area>.<name> improves searchability.

L (Local) Memory in TIA Portal V11 SP2

The S7-1200 supports local tags declared inside a code block (OB, FB, FC) with the Local keyword. Local memory lives in the L stack and is consumed while the block executes.

Declaring a local

1. Select the FB/FC/OB.
2. In the upper section declare a new row; choose Temp for transient data or Static for instance data.
3. Enter a name, datatype and start value. Example for a toggling FB:

FB "ToggleFB" - Interface
VAR_TEMP
    tInputEdge   : BOOL;    // rising edge of the call input
    tState       : BOOL;    // toggled value
    tLastInput   : BOOL;    // edge memory
END_VAR

Accessing locals from LAD/FBD

In TIA Portal V11 SP2 the local tags are visible only in the interface editor and in code blocks that are inside the same FB/FC. They are deliberately hidden from the project-wide tag table - that is the reason local memory is safe against accidental reuse.

Common pitfalls with L stack in V11 SP2

• If a multi-instance FB is instantiated inside another FB without its own DB, the V11 SP2 compiler emits a Multiple instance DB required warning. Resolve by enabling Properties > Compilation > Single instance DB or supplying a multi-instance DB.
• Temporary variables initialized with a value lose that value on the next call of the same FC. Do not use temporaries for counter or state bits.
• Renaming a local variable invalidates references in libraries cached in TIA Portal V11 SP2. Clean the project (Project > Compiler > Show information > Rebuild all) before reinstalling the libraries.

TIA Portal V11 SP2 Project Compatibility

TIA Portal V11 SP2 introduced the binary project container .ap11; legacy SIMATIC Manager projects (Step 7 V5.x) end in .s7p or are stored in a Step 7 archive *.zip. A direct open is not supported. To migrate: launch Step 7 V5.5, select the project, choose File > Save as > Migration export, then open the migrated file in TIA Portal V11 SP2 through Project > Migrate project. Libraries delivered as .s7l (Step 7 V5.x Library) cannot be opened in TIA V11; they must be converted with the S7 Library Migration tool that ships with TIA V11 SP2 Update 2.

Verification Checklist

After any change to RUN/STOP logic, scan guard, or block interface, validate with the table below.

Troubleshooting Matrix

Frequently Asked Questions