S7-1200 Positive Edge Detection Resetting P_TRIG with M-Bit

Overview

The SIMATIC S7-1200 CPU family handles positive edge detection fundamentally differently from the legacy S7-200. On the S7-200, a positive edge contact -(P)- or P_TRIG instruction was self-resetting: the output remained TRUE for exactly one OB1 scan and then cleared automatically because the edge memory bit was managed internally by the firmware. On the S7-1200, edge detection is explicit. The programmer must assign a dedicated edge memory bit (typically from the M or DB area) to hold the previous state. If no memory bit is wired correctly, the instruction either latches indefinitely, fires on PLC startup when the input is already TRUE, or never fires at all.

This article explains the internal mechanics, the correct wiring pattern in TIA Portal V15 and later, and the verification procedure to confirm one-scan positive edge behavior. It also covers the related negative edge (-(N)- / N_TRIG) and the IEC 61131-3 function blocks R_TRIG / F_TRIG.

Prerequisites

• SIMATIC S7-1200 CPU (any firmware version; behavior is consistent from FW 4.0 through FW 4.6+)
• TIA Portal V15.1 / V16 / V17 / V18 or STEP 7 Basic in the matching version
• Familiarity with the LAD (Ladder Diagram) or FBD (Function Block Diagram) editor
• A free marker byte in the M area, or a free BOOL tag in a global DB
• Wiring verified: input module (DI) terminal block connected, sensor powered, 24 V DC on the input channel

Why the S7-1200 Differs from the S7-200

The S7-200 firmware allocated an internal, hidden edge memory buffer (commonly cited as 256 bits per scan) for its -(P)- contacts. Each instance of the edge instruction implicitly drew one bit from this hidden pool. The programmer never saw or managed the bit; the system handled it. This is why S7-200 edge contacts behaved as a clean one-shot.

The S7-1200 abandoned the hidden pool model. Per the SIMATIC S7-1200 Programmable Controller Manual Collection, section "Positive and negative edge instructions", the CPU compares the current state of the input operand to the state stored in an explicit edge memory bit. If both were FALSE on the previous scan and the input is TRUE on the current scan, a rising edge is detected and the instruction's Q output is TRUE for exactly one program cycle of OB1.

The catch: the edge memory bit must be uniquely associated with that one edge instruction. Reusing the same bit elsewhere corrupts the detection, and using a local (Temp) variable instead of a global marker causes the bit to reset on every block call, producing the latched-ON symptom most users encounter.

Edge Detection Fundamentals in S7-1200

An edge is the transition of a BOOL signal between two states:

• Positive (rising) edge: FALSE → TRUE. Instruction mnemonic -(P)- or function block P_TRIG / R_TRIG.
• Negative (falling) edge: TRUE → FALSE. Instruction mnemonic -(N)- or function block N_TRIG / F_TRIG.

Detection requires two storage slots:

1. Current state — read live from the operand on every scan.
2. Previous state — stored from the prior scan in the assigned edge memory bit.

The detection logic is:

IF (current = TRUE) AND (previous = FALSE) THEN
    output Q := TRUE;        // one scan only
    previous := TRUE;        // store for next comparison
ELSE
    output Q := FALSE;
    previous := current;     // store for next comparison
END_IF;

The output Q is TRUE for a single OB1 cycle even if the input remains TRUE. This is identical in spec to the S7-200; the difference is that on the S7-1200 the previous-state bit must be assigned, and the CPU does not clear the Q for you if the wiring is wrong.

Method 1 — P_TRIG / R_TRIG Function Block (Recommended)

For a S7-1200 with firmware V4.0 and later, the IEC 61131-3 compliant P_TRIG (or its alias R_TRIG) function block is the preferred method. It encapsulates the edge memory bit inside an instance data block, eliminating the risk of a programmer assigning the same M-bit to two instructions.

Wiring procedure:

1. In TIA Portal, open the OB1 (or the destination network) in the LAD/FBD editor.
2. From the instruction catalog, navigate to Basic Instructions → Bit Logic Operations → Edge detection.
3. Drag P_TRIG into the network.
4. Click the CLK input, type the process input, e.g. %I0.0 (the sensor input).
5. Click the Q output, type the destination tag, e.g. "EdgeSensor" (a local or global BOOL).
6. Right-click the P_TRIG block header and select Generate instance DB. Accept the default name (e.g. iEdge_P_TRIG_1).
7. Compile and download.

Each P_TRIG instance DB contains one internal BOOL named CLK_OLD. The firmware updates CLK_OLD automatically on every call. The block is single-instance per call site: do not call the same instance DB from two networks.

Method 2 — -(P)- Contact with M-Bit

The -(P)- contact is a shorthand that exists for source compatibility with S7-200 / S7-300 STL habits. It is functionally identical to P_TRIG but the edge memory bit is exposed as a separate operand on the contact.

Wiring procedure:

1. Open the network in LAD.
2. Drop a Normally open contact from the toolbar — this becomes the edge contact only if you select P on the contact properties.
3. Alternatively, type directly: "Signal1" "M11.3" -(P)-. The first operand is the trigger input; the second is the edge memory bit.
4. Use a unique M-bit per -(P)- contact. Reserve a marker byte (e.g. MB10 .. MB20) exclusively for edge memory.

Network 1
    %I0.0        M11.3
---|-|-----(P)----------( "EdgeFlag" )---

Rules for the M-bit selection:

• Bit must be in the M area or a global DB. Local TEMP bits are forbidden.
• Bit must not be written anywhere else in the program. Touching the bit elsewhere defeats the edge memory.
• Bit must not be reused for a second edge instruction, even of different polarity.
• Retentive or non-retentive setting is irrelevant; either works. Non-retentive is safer because a power-cycle gives a known-cold state.

Resolving the Latch-ON Symptom

The most common fault report on the S7-1200 is: "The edge contact stays ON as long as my input is ON." This is not a firmware bug; it is one of three configuration errors.

The PLC-Startup Pitfall

A particularly confusing behavior is: "When I power up the PLC with my sensor already on, the Q output is set immediately". On the S7-200, this would not happen because the internal edge memory buffer was initialized to FALSE at startup. On the S7-1200, the edge memory bit retains its last value if it sits in a retentive M-bit area, or it can be undefined if the M-bit is in a non-retentive area that was never initialized.

Recommended fix:

1. Place the edge memory bit in a non-retentive marker byte. In TIA Portal, open PLC tags → Show all tags, expand the M area, and confirm the Retain column is unchecked for the edge byte.
2. Use the startup OB (OB100 for warm restart, OB101 for hot restart) to explicitly reset all edge memory bits: SET M11.0 .. M11.7 := FALSE; using an SCL snippet or a finger-of-FBD R coil on each bit.
3. For critical applications, gate the trigger with an EN input that becomes TRUE only after the first full OB1 cycle. This is implemented with a startup-flag bit set in OB100 and cleared in OB1 on its second pass.

Step-by-Step: Reproducing S7-200 Behavior in TIA Portal

Goal: detect a rising edge on %I0.0 and set "OneShot" TRUE for exactly one OB1 cycle.

1. Open your project in TIA Portal V17 (or V18).
2. Add a new FB or open OB1.
3. Insert a P_TRIG block from the catalog. If you cannot find it, type P_TRIG directly into an empty FBD box; the autocompleter resolves it.
4. Wire %I0.0 → CLK. Wire "OneShot" ← Q.
5. Accept the auto-generated instance DB iPTRIG_DB1.
6. Place a normally open contact "OneShot" on a downstream network. Wire it to a Set coil on "OutputQ" (or any BOOL tag you wish to latch).
7. Compile (Project → Compile all) and download to the CPU.
8. Go online, force %I0.0 TRUE for 5 seconds. Observe in the monitor: "OneShot" must flash TRUE for one scan (the column shows TRUE on a single row in the cross-reference watch table).

Verification Procedure

After commissioning, perform the following three checks using a watch table and online monitoring:

1. One-scan width test: Force the trigger input TRUE; open the watch table on the edge Q bit. The bit must display TRUE for one observation, FALSE on the next. If it stays TRUE, the edge memory bit is contaminated (see table above).
2. Re-trigger test: Force input FALSE, then TRUE, then FALSE, then TRUE in succession. Each TRUE transition must produce exactly one TRUE pulse on Q. A double pulse indicates shared M-bit memory.
3. Power-cycle test: With the input held TRUE, perform an MRES or power cycle the CPU. On restart, the Q bit must remain FALSE until the input transitions FALSE → TRUE again. A set Q on restart indicates non-retentive edge memory was not initialized in the startup OB.

Edge Bit Memory: Sizing and Limits

Method Comparison

Common Fault Patterns and Diagnostics

Use the TIA Portal online Monitor & Force and Cross-reference views to triage. The following matrix maps observable symptoms to underlying cause:

Implementation Patterns

For routine use across a large project, define an edge memory convention in the project header:

// Project edge memory convention (example)
// MB100 .. MB109: Positive edge memory (80 bits available)
// MB110 .. MB119: Negative edge memory (80 bits available)
// Each -(P)- / -(N)- consumes one bit; do not reuse.
// All bits in this area are non-retentive (Retain = FALSE).
// OB100 clears MB100 .. MB119 to 0 on every restart.

For a structured SCL approach, the function block pattern is cleanest:

FUNCTION_BLOCK "fbEdgeCounter"
VAR
    iTrig : R_TRIG;          // rising-edge instance
    iCount : INT;
END_VAR

BEGIN
    iTrig(CLK := "SensorInput");
    IF iTrig.Q THEN
        iCount := iCount + 1;
    END_IF;
    "EdgeCount" := iCount;
END_FUNCTION_BLOCK

The R_TRIG instance is held in the function block's instance DB, so the edge memory bit lives with the block. Multiple calls to fbEdgeCounter each get their own instance and therefore their own edge memory.

References Within the Article

• SIMATIC S7-1200 Manual Collection — Positive and negative edge instructions
• Siemens Industry Online Support — Detect positive signal edge (S7-1200, S7-1500) entry 109747174