Porting S7-300 STL to S7-1200 TIA Portal: SCL Conversion Guide

Overview

The SIMATIC S7-1200 controller family does not compile or load programs written in Statement List (STL/"AWL") that were authored for the SIMATIC S7-300/S7-400 generation. STL is intentionally excluded from the S7-1200 instruction set; the supported languages are Ladder Diagram (LAD), Function Block Diagram (FBD), and Structured Control Language (SCL). Direct import of compiled STL blocks from STEP 7 V5.x into the S7-1200 controller is therefore impossible. Migration must follow one of two engineering paths:

1. Manual/Assisted rewrite: re-author the original algorithm in LAD, FBD, or SCL inside TIA Portal.
2. SCL conversion: port the STL logic to SCL, which is a textual, high-level Pascal-style language available on S7-1200 CPUs from firmware V4.0 onward. Earlier S7-1200 firmware versions required V2.2.0 for SCL activation.

This reference describes the technical boundary between S7-300 STL and S7-1200, the firmware and toolchain prerequisites, a deterministic conversion procedure, and the verification checks that confirm a ported FB/FC operates identically on the target CPU.

S7-1200 Programming Language Matrix

The following table summarizes language availability on each Siemens controller generation relevant to a migration. Items marked with an X are supported natively; items marked with a footnote indicate conditional support.

Prerequisites for Migration

CPU Firmware Requirements

SCL on the S7-1200 first appeared in firmware version 2.2.0, released alongside STEP 7 (TIA Portal) V11 SP2. New features bundled with FW V2.2.0 include:

• SCL (Structured Control Language) compiler/runtime.
• Download in RUN (program changes while the CPU is in RUN mode).
• CM 1243-2 AS-i Master.
• CM 1241 RS422/485 communication module.
• SM 1222 DQ8 RLY Changeover.

Current S7-1200 CPUs in production ship with firmware V4.2.x or later. SCL is fully integrated; no optional authorization is required. Confirm the firmware level before rewriting blocks:

1. Open the device configuration in TIA Portal.
2. Right-click the CPU and select Online & Diagnostics.
3. Read the firmware version from the device.
4. If FW is below 2.2.0, perform a firmware update via Online > Accessible Devices using an SD card or directly over Ethernet.

Engineering Toolchain

STL versus SCL: Conceptual Mapping

STL is a low-level, accumulator-based language. The CPU exposes two 32-bit accumulators (ACCU1, ACCU2) and a status word that drives conditional jumps. SCL is a high-level, structured-text language with explicit variable types, automatic code optimization, and a Pascal-like syntax. The mapping is not one-to-one and requires deliberate rework in three areas:

1. Operand handling: STL's accumulator-explicit moves (L, T) collapse into SCL assignment expressions.
2. Control flow: STL jump labels (JU, JC, JN, JZ, JN, JP, JM, JZ, JO) are replaced with structured IF, CASE, FOR, WHILE, and REPEAT statements.
3. Indirect addressing: STL's memory-indirect and register-indirect addressing (see Indirect addressing in STL (S7-300, S7-400)) maps to SCL array index expressions or pointer-based access via PEEK/POKE and AT notation.

Mnemonic Translation Table

Indirect Addressing Conversion

The S7-300 STL modes documented in Indirect addressing in STL (S7-300, S7-400) have three flavors:

1. Direct addressing: L MW 10 (always MW10).
2. Memory-indirect: L MW [MD 20] (uses pointer in MD20).
3. Register-indirect area-internal: L MW [AR1, P#0.0] (uses AR1 with displacement).
4. Register-indirect area-crossing: L W [AR1, P#0.0] (data block and pointer both come from AR1).

SCL Patterns for Indirect Access

Convert each STL indirect pattern to one of these canonical SCL forms. Use a typed tag array so the compiler can validate indexes.

// STL:  L DBW [MD 100]   (memory-indirect via MD100)
// SCL:  iValue := "Data".Word["MD100"]; // MD100 holds DWORD index

// STL:  AUF DB 200
//       L DBB [AR1, P#4.0]
// SCL:  iValue := "MyDB200".Byte[BYTE#4];  // or via AT view

// Array-based loop replaces pointer arithmetic
FOR i := 0 TO 99 BY 1 DO
    IF "RecipeDB".Temp[i] > 1000 THEN
        "RecipeDB".Out[i] := TRUE;
    END_IF;
END_FOR;

Step-by-Step Conversion Procedure

Step 1 - Extract Source Blocks from STEP 7 V5.x

1. Open the S7-300 project in STEP 7 V5.5 or V5.6.
2. Expand Blocks and identify every OB, FB, FC, DB, UDT, and SFB call required.
3. Right-click the block and choose Generate Source File to obtain .STL/.SCL text.
4. Cross-reference inputs and outputs against the hardware list to capture used I/O, markers (M), and DBs.

Step 2 - Inventory Migration Units

Before touching TIA Portal, build a migration register. Each row defines one block to be rewritten.

Step 3 - Build the S7-1200 Project Skeleton in TIA Portal

1. Create a new project, Add New Device > SIMATIC S7-1200 > CPU 1214C DC/DC/DC (or your target MLFB such as 6ES7214-1AG40-0XB0).
2. Configure the rack with the matching signal modules from the S7-300 hardware list.
3. Define the PLC tags: PLC tags > Default tag table. Create I/O tags for I, QB, IW, MW areas carried over from the legacy project.
4. Add the program blocks folder and create placeholders for each FB/FC listed in the inventory.

Step 4 - Rewrite Each Block to SCL

1. Open the new block in SCL by selecting the language when creating it.
2. Translate STL statement-by-statement using the mapping table above. Adhere to these conversion rules:
   • Variable declarations move to the block interface (Input/Output/InOut/Static/Temp).
   • Replace any SAVE with explicit assignment to ENO when required.
   • Replace SET/CLR with TRUE/FALSE literals.
   • Convert AUF DB x to either an instance DB reference or a fully qualified tag like "MyDB".Field.
   • Replace unconditional jumps with structured control flow.
3. Compile the block. Resolve every warning before proceeding. Errors commonly reported:
   • Unknown identifier: missing interface declaration.
   • Type mismatch: DWORD vs WORD when STL used overloaded 16/32-bit operations.
   • Implicit pointer conversion: requires DWORD_TO_INT etc.

Step 5 - Re-create Data Blocks

On the S7-1200, default DBs are optimized (symbolic only). Two migration choices:

• Keep DB structure compatible: set the DB to non-optimized (compatibility mode) and tick "Memory area must be retentive" only where legacy used retentivity. Symbolic addressing remains available.
• Move to optimized: rewrite DB accesses as "MyDB".Variable and rely on symbolic bound names. Faster access; no dual-fold image.

Time and Counter Objects

STL's SV, SE, SS, and SA timer commands and the legacy counter commands (CU, CD, C) execute on internal system functions that differ architecturally between S7-300 and S7-1200. The S7-1200 exposes the IEC timers TP, TON, TOF, TONR as multi-instance FBs inside the system library "TIMERS". Convert each legacy timer/counter as in the examples below.

// STL:    L    S5T#2s
//         SE   T 10
// SCL:    "IEC_Timer_0".SE := FALSE;
//         "IEC_Timer_0".TP(IN := bStart,
//                          PT := T#2s,
//                          Q  => bQ,
//                          ET => tET);

// STL:    CU   Z 5
// SCL:    "IEC_Counter_0".CU := bPulse;
//         "IEC_Counter_0".CU_CNT := TRUE;

Diagnostics and Watch Tables

After rewriting, build a watch table to confirm the SCL implementation matches the legacy STL logic.

1. Watch tables > Add new watch table.
2. Insert every input byte (IBx), output byte (QBx), and intermediate marker (MWy) consumed by the block.
3. Trigger force on a controlled input (e.g., "I0.0") and confirm expected MW changes.
4. Use a trace (CPU FW V4.0+) to capture cyclic execution of the rewritten SCL block and compare against stored traces from the original S7-300 if any.

Troubleshooting Matrix

Verification Procedure

1. Compile check: TIA Portal > Project tree > Program blocks > right-click > Compile all. Expect zero errors and zero warnings.
2. Online compile consistency: connect online; right-click PLC > Compare online/offline. Differences must be empty.
3. Single-step test: place the program in single-step via project properties (only available on certain FW variants) or insert breakpoint equivalents using monitor with test.
4. Functional black-box test: simulate inputs, capture outputs, compare with stored S7-300 expected values.
5. Long-term diagnostic buffer review: cycle the CPU for at least one production shift (or simulation equivalent). Inspect the diagnostic buffer for OB82 / OB121 / OB122 events.

Appendix - Data Type Compatibility

Frequently Asked Questions