S7-1200 System and Clock Memory Not Working in TIA Portal PLCSIM

Configuring System memory bits and Clock memory bits in the CPU properties of a SIMATIC S7-1200 is a five-second operation, but the bits often appear "dead" inside PLCSIM (the TIA Portal simulator) even when the enable checkbox is clearly ticked. This article documents the exact root cause, the verification path, and the architectural alternatives that eliminate the symptom permanently.

1. Problem Description

The reported symptoms are consistent across multiple field cases:

1. The user opens CPU Properties → System and clock memory in the TIA Portal device configuration.
2. The user enables the checkboxes "Enable system memory byte" and "Enable clock memory byte", optionally changing the byte address from the default (typically MB0 / MB1 on S7-1200).
3. The program is compiled and downloaded to PLCSIM.
4. The bits at the configured addresses never toggle, the FirstScan bit never returns TRUE, and the clock bits stay FALSE indefinitely.

The hardware configuration download is the most frequent missing step; the program blocks alone do not carry the CPU properties that govern system/clock memory. PLCSIM emulates the firmware behavior of a real CPU, and without a coherent system data block the firmware never allocates the clock generator or the first-scan latch.

2. Root Cause Analysis

Three root causes account for >95% of "clock memory not working" tickets in the S7-1200 platform:

3. System Memory vs Clock Memory - Technical Foundation

System memory and clock memory are two independent byte resources. The CPU firmware generates them on every cycle of OB1 regardless of user code; they exist in the process image and are refreshed before OB1 reads them.

3.1 System memory byte (S7-1200, fixed bit map)

3.2 Clock memory byte (S7-1200 / S7-1500, standard pattern)

3.3 Inline timing diagram

Figure 1. Clock memory bit waveforms over a 3-second window. Bit 0 of the clock byte toggles ten times per second; bit 5 is a 1 Hz heartbeat; bit 7 produces a 2-second period used for human-visible status lamps.

4. Prerequisites

• Installed and licensed TIA Portal V16 or later (V17 / V18 / V19 supported).
• Installed PLCSIM V16+ (PLCSIM V2 is end-of-life since TIA V15.1 and does not implement system/clock memory in the same way).
• Configured S7-1200 CPU in the project tree (the system/clock memory checkboxes are part of the device configuration, not the program blocks).
• PG/PC interface route to PLCSIM either via PLCSIM Virtual Ethernet Adapter (PLCSIM V16+) or the TCP/IP route SIEMENS PLCSIM.

5. Step-by-Step Resolution

Execute the following sequence. Step 4 is the canonical fix for the "PLCSIM clock memory not working" symptom.

1. Open the device configuration. In the TIA Portal project tree, double-click Devices & networks → CPU_1 [CPU 1214C DC/DC/DC].
2. Open CPU properties. Select the Properties tab in the inspector, then navigate to System and clock memory (or in older TIA versions, System and clock memory under the General node).
3. Enable the bytes and select addresses. Tick "Enable the use of system memory byte" and "Enable the use of clock memory byte". Set the system memory byte to a non-retentive address (e.g. MB1000) and the clock memory byte to MB1001. Avoid the default MB0 / MB1 on S7-1200 because the first two bytes fall inside the retentive range typically set in PLC → Retentive memory.
4. Compile the hardware configuration. Right-click the CPU in the project tree and select Compile → Hardware (rebuild all). This regenerates the system data blocks (SDB 100, SDB 0, and the IO configuration) that PLCSIM needs to instantiate the clock generator.
5. Start PLCSIM and download the entire device. Click Online → Download to device. In the dialog, select PG/PC interface = PLCSIM, choose Configured interface = TCP/IP, click Start search, and select the discovered PLCSIM instance. Ensure the "Download to device" group has both Hardware configuration and Software (all blocks) selected. Press Load and confirm the dialog that says "Download of hardware configuration to device".
6. Restart PLCSIM if the CPU is already RUN. If PLCSIM was running before step 5, do Online → Stop CPU, then Online → Run CPU. The system memory and clock memory bits are only re-initialized on STOP→RUN or power-on.
7. Verify in a watch table. Open a new watch table, enter "Clock_Memory_Byte" (default name: Clock_1 or your custom tag) and the FirstScan bit at %MB1000.0. Toggle the value format to Binary. The FirstScan bit will be TRUE for one cycle after restart; the Clock 200 ms bit at %MB1000.4 will toggle at 5 Hz.

6. Alternative Architecture: Clock Bits in a Global DB with Cyclic Interrupt OBs

For projects that follow a strict no-M-area coding style, the system/clock memory can be replaced by a Global Data Block driven by a Cyclic Interrupt OB. The benefit is full type-safety, searchability (Ctrl+F finds "Heartbeat" in seconds), and zero overlap risk with retentive memory.

6.1 DB definition

DATA_BLOCK "GlobalClock"
{ S7_Optimized_Access := 'TRUE' }
VERSION : 0.1
NON_RETAIN
  STRUCT
    Heartbeat_10Hz   : BOOL;   // 100 ms period
    Heartbeat_5Hz    : BOOL;   // 200 ms period
    Heartbeat_2Hz    : BOOL;   // 500 ms period
    Heartbeat_1Hz    : BOOL;   // 1 s period
    FirstScan        : BOOL;
    AlwaysTRUE       : BOOL;
    AlwaysFALSE      : BOOL;
    DiagStatusChanged: BOOL;
  END_STRUCT;
END_DATA_BLOCK

6.2 OB30 - 100 ms cyclic interrupt (configurable in CPU properties → Cyclic interrupts)

// OB30 - Cyclic interrupt, 100 ms
"GlobalClock".Heartbeat_10Hz := NOT "GlobalClock".Heartbeat_10Hz;
IF "GlobalClock".Heartbeat_10Hz THEN
  "GlobalClock".Heartbeat_5Hz := NOT "GlobalClock".Heartbeat_5Hz;
  IF "GlobalClock".Heartbeat_5Hz THEN
    "GlobalClock".Heartbeat_2Hz := NOT "GlobalClock".Heartbeat_2Hz;
    IF "GlobalClock".Heartbeat_2Hz THEN
      "GlobalClock".Heartbeat_1Hz := NOT "GlobalClock".Heartbeat_1Hz;
    END_IF;
  END_IF;
END_IF;

6.3 OB100 - FirstScan handling

// OB100 - Startup (warm restart)
"GlobalClock".FirstScan := TRUE;
// OB1 user code must reset it on the first cycle:
// "GlobalClock".FirstScan := FALSE;

When this architecture is adopted, the system/clock memory canisters in the CPU properties can stay disabled, freeing the M area for a dedicated, well-documented Global DB that holds all data exchange between machine sections, HMI, alarms, and setpoints.

7. Memory Layout, Retentivity, and Overlap Hazards

On every S7-1200 CPU the M area default retentive range starts at MB0 and has a length of 8 bytes (MB0..MB7) on a CPU 1211C/1212C, 14 bytes on a CPU 1214C, and more on the larger variants. If the system memory byte is placed in that range, the following overlap hazards exist:

Recommended placement on S7-1200. CPU 1214C provides 8 KB of M area (0..8191). Place system memory at MB1000 and clock memory at MB1001; the symbolic tags can be defined as "SysMemByte" and "ClockMemByte" in the PLC tag table. This range sits well above the default retentive cutoff and is far from the IEC timer/counter, I/O process image, and DB base areas.

8. Verification and Commissioning

After the fix, run the following verification sequence on every project:

1. Watch table check. Add the configured clock memory byte as binary. The pattern should be a stable, 50% duty-cycle square wave. The period at bit 5 must measure 1000 ms ± 1 ms in the online trace.
2. FirstScan check. Force a STOP→RUN transition. In OB1, the FirstScan bit must be TRUE for exactly one OB1 cycle. Use a one-shot FP (rising-edge) on the tag to confirm.
3. OB1 cyclic time check. Use Online → Diagnostics → Cycle time to confirm OB1 is running. A CPU that is stuck in STOP will leave clock memory frozen at the last state.
4. Hardware configuration consistency check. In PLCSIM V16+, use Online → Accessible nodes → Flash LED on the simulated CPU to confirm the system data blocks were applied.
5. Retentivity boundary check. Place a breakpoint in OB1 on a marker just above the retentive range. Cold restart, warm restart, and STOP→RUN should all yield the same FirstScan=TRUE on the first cycle.

9. Troubleshooting Matrix

10. Best Practices for M-Area Usage

• Treat the M area as transient scratch memory. Anything that needs to survive STOP→RUN, power off, or cold restart belongs in a retain-tag DB.
• Use symbolic names from day one. Define Clock_1Hz, Clock_5Hz, FirstScan in the PLC tag table; raw M references are not searchable and not refactorable.
• Reserve a memory map. Document the M area usage in a project-wide Memory Map sheet. The first 100 bytes for "high-speed markers", 100..200 for "handshake flags", 1000..1001 for "system/clock memory".
• Disable retentivity for the M area unless the application genuinely needs it. The default on S7-1200 is retentive for MB0..MBx; a tighter retentive range reduces "stuck bits" issues during PLCSIM debugging.
• Prefer a Global DB architecture for any project above ~10 kB of program memory. The CPU's M area is a finite resource (8 KB on CPU 1214C, 16 KB on CPU 1217C), and the symbolic DB approach scales into the S7-1500 port.
• Never start a 32-bit instruction at MB0. A single L MD0 in OB1 will silently corrupt system/clock memory; this is the single most common overlap bug in field code.
• Cross-reference before every download. Project tree → CPU_1 → Cross-references; filter for System and clock memory to see what user code touches those addresses.

11. Specifications Reference