S7-400 vs S7-300 PID Performance Selection for Critical Loops

Overview: Positioning the SIMATIC Families

Engineers selecting a SIMATIC controller for closed-loop control routinely face the same question: does a higher-tier CPU actually deliver measurably better PID behavior, or is the price delta paying only for memory, I/O count, and communications? This reference consolidates the architectural differences between the S7-1200, S7-300, and S7-400 families, evaluates their PID execution models, and provides a field-proven selection matrix for installations where a few loops govern process safety (e.g., glass furnaces, burner management, exothermic reactors).

The 32-bit architecture, larger working memory, and the optional CPU 410 variant place the S7-400 in a class above the S7-300, but the practical superiority for a small number of loops is often debated. The discussion below separates marketing language from engineering reality, drawing on the public SIMATIC S7-400 reference manual and the PCS 7 catalog data.

Architectural Comparison: S7-1200 vs S7-300 vs S7-400

All three platforms share the STEP 7 / TIA Portal programming model, but the silicon and backplane differ substantially. The table below summarizes the parameters that matter for closed-loop control.

Bit-execution time alone does not decide PID quality. The cycle architecture, the priority class of the OB that calls the PID block, and the deterministic scheduling of analog input refresh all matter. The S7-400 maintains a separate process image partition and supports OB 30–OB 38 time-of-day / cyclic interrupt OBs at intervals from 1 ms upward; the S7-1200 supports four cyclic interrupt OBs (OB 200–OB 204) with a minimum period of 1 ms, and the S7-300 supports OB 30–OB 38 down to 1 ms as well.

PID Implementation Models in SIMATIC

Siemens supplies two implementation philosophies. The TIA Portal "Compact" blocks use a fixed-cycle API optimized for low overhead; the older STEP 7 "Standard" blocks give the engineer full control over cycle time, anti-windup, and bumpless transfer. Understanding the block family is the first step to diagnosing loop quality differences.

The fundamental discretization equation is identical in every block:

where T_s is the controller cycle time. Because the I-term uses rectangular integration and the D-term uses a velocity form, the loop quality depends on the ratio of T_s to the plant dominant time constant. The longer the cycle, the larger the discretization error and the more visible the load disturbances. This is the engineering reason the S7-400 and S7-410 family is preferred for thermal and mass-flow loops with time constants in the seconds range: a 100 ms controller scan on CPU 410 versus a 1 s scan in legacy tuning makes the proportional + integral term behave like the continuous-time ideal by a factor of ten.

Scan Time vs. Throughput: What Actually Improves Loop Behavior

Three distinct timing concepts determine closed-loop performance:

1. OB 1 cycle time — the round-trip time of the main user program.
2. Analog input refresh — how often the channel data is updated in the process image. S7-400 SM 431 modules update at 1.7–20 ms per channel depending on integration time; S7-300 SM 331 averages 9–100 ms per channel based on the configured noise rejection (50/60 Hz).
3. PID sample time T_s — the rate at which the controller re-evaluates the error. This is set inside the PID block and is independent of OB 1.

The S7-400 with a 1–3 ms OB 1 cycle provides headroom to schedule PID blocks in OB 30 at 100 ms while the user program continues to scan in OB 1 without overrun. The S7-1200, with a 10–40 ms OB 1 cycle, must be tuned carefully to ensure the cyclic interrupt OB has higher priority and that no I/O conversion stalls the analog channel. S7-300 sits between the two.

CPU 410 and the DCS Positioning

Siemens markets the CPU 410 SMART / CPU 410-5H (and its PCS 7 derivative, the AS 410) as an "AS-class" controller bridging PLC and DCS markets. Three concrete differences from a standard S7-400 CPU are listed in the SIMATIC PCS 7 catalog:

• Fixed task cycle model. The user program is built as a CFC chart library. The scan is divided into time slices of typically 100 ms, 500 ms, 1 s, 5 s, and 10 s. There is no free-wheeling OB 1, no arbitrary user ladder, and no "fast" OB 30 inserted in user code.
• Charts only — no block download. Compiled units (SCL/FB/SFC) cannot be downloaded individually. The entire chart program compiles to a single runtime file. This forces a controlled change-management workflow (CFC delta download) that DCS operators require.
• Subsample / time-quantum interpolation. Because the base scan is long (1 s by default for CTRL_PID), the controller block does not run on the "obvious" 1 s boundary. It sub-samples at a configurable multiple of the OB 36 task and interpolates analog inputs, achieving a 100 ms effective loop time with stable CPU load.

These features are not present in a generic S7-400 CPU used with STEP 7, but the controller resolution in milliseconds is comparable. The relevance for our question is that CPU 410 ships with a stricter execution contract: predictable scan, controlled download, redundancy-ready backplane, hot-swap, and pre-engineered PID/sequence/asset blocks.

Is the S7-400 a Parallel-Processing CPU?

A claim circulates that the S7-400 "processes analog inputs in parallel so 100 PID loops behave as well as one." This is partly true and partly misleading. The hardware does not have a true multi-core processor. What it does have is:

• Multiple OB priority classes. Cyclic interrupts (OB 30–OB 38) preempt the main scan; time-of-day OBs (OB 10–OB 17) preempt the cyclic; hardware interrupts (OB 40–OB 47) preempt all of the above.
• Time-slice scheduling of PID charts. The PCS 7 dispatcher can run, for example, 16 critical loops in OB 36 at 100 ms, 32 mid-priority loops in OB 35 at 500 ms, and the remainder in OB 34 at 2 s. Each loop sees a deterministic interval, and the discrete-time approximation error of any single loop is identical to that of an isolated controller running at its assigned rate.
• Dedicated analog hardware. The S7-400 SM 431 high-speed modules can convert eight channels in 0.4 ms total (24-bit, 0.1 ms/ch with 50 Hz rejection disabled) which the S7-300 SM 331 cannot match in channel density.

The net effect is that loop 100 does not degrade loops 1–99 as long as the user assigns each loop a sensible T_s and the OB cycle supports it. The same scheduling is achievable on an S7-300 with sufficient care, but the S7-400 makes the trade-off explicit and reserves execution budget for it.

Selection Matrix for Critical PID Applications

Case Study: Glass Furnace Loops on a 32 PID CPU 410

Glass furnaces typically present 4–6 closed loops whose failure modes are not recoverable: a runaway gas/air ratio on a regenerative furnace will collapse the crown and pull the superstructure down. A typical control structure is:

• Loop 1: Furnace pressure (draft) — τ ≈ 5–15 s, T_s = 200 ms.
• Loop 2: Glass level (laser/optical level sensor) — τ ≈ 60–180 s, T_s = 1 s.
• Loop 3: Combustion gas flow — τ ≈ 1–3 s, T_s = 100 ms.
• Loop 4: Combustion air flow (cross-limited) — τ ≈ 1–3 s, T_s = 100 ms.
• Loop 5: Forehearth temperature (zone-by-zone) — τ ≈ 600 s, T_s = 5 s.

The fast loops (3 and 4) require sub-second cycle times to track load transients in airflow that follow glass batch charge events. A CPU 410 with PFC/CTRL_PID blocks subsampled at 100 ms, on a 1 s base scan, gives a stable I-term and a properly damped D-term. The same loops on an S7-1200 with PID_Compact configured at 100 ms will work, but a 10–40 ms OB 1 cycle is too noisy for the high-frequency pressure loop when more than 8 PID blocks run in parallel.

S7-300 vs S7-400 When Neither Redundancy nor DCS Workflow Is Required

When a plant needs 4–10 PID loops, no redundant CPU, no PCS 7 workstation, and no CFC workflow, the S7-300 with a CPU 319-3 PN/DP is frequently a defensible choice. The CPU 319 provides:

• 1.4 MB of work memory, 8 MB load memory.
• Bit execution in ~50 ns.
• PROFINET IRT capable PN interface, PROFIBUS-DP master for distributed I/O.
• Up to eight cyclic interrupt OBs in the OB 30–38 range.
• Mature library of FB 41 (CONT_C) used in 100 000+ installations.

Where the S7-400 wins is the OB scheduling depth (OB 30–38 with down to 1 ms period, and OB 121–OB 122 synchronous error OBs that the S7-300 handles less gracefully) and the headroom for additional user program. For a four-loop application, the S7-400 is "premium but not strictly necessary." The S7-1500 is now the better long-term investment unless the plant has an installed base of S7-300 PROFIBUS peripherals.

S7-1200 Limitations for Critical PID

The S7-1200 is fully capable of closed-loop control, but three practical limits appear in field installations:

1. Analog channel conversion latency. The onboard SM 1231 updates at 625 μs per channel but the cycle OB cannot drive the controller faster than 1 ms. The PID_Compact block has a lower limit on T_s (typically 50 ms) enforced by the firmware.
2. OB 1 cycle jitter. Without explicit priority control, an overloaded OB 1 will extend the cyclic interrupt phase and miss scheduled PID ticks. Commissioning must include a worst-case cycle-time measurement with the OBs at 100% and all alarms enabled.
3. No integrated redundancy. The S7-1200 cannot form a hot-standby pair. For processes where a PLC fault is not tolerable, the S7-400H or CPU 410-5H is the only Siemens path.

Modernization Path: S7-1500 and TIA Portal

For new installations the S7-1500 supersedes both the S7-300 and the S7-400 in non-redundant scopes. The CPU 1518-4 PN/DP, for example, executes bit operations in 1 ns, has 30 MB of work memory, and integrates OPC UA server plus security functions. The PID block family is PID_Compact (V2), PID_3Step (V2), and PID_Temp for thermal profiles. S7-1500T extends with motion. S7-1500R/H is the redundant pair for soft-redundancy hot standby.

The S7-400 line, while still supported, is no longer the recommended path. The SIMATIC S7-400 product discontinuation announcement (PM410/2018) lists the controller as on "phase-out" with a final spare-part horizon.

Commissioning Checklist for Critical Loops on S7-400 / CPU 410

1. Verify OB 1 worst-case cycle with Watch Table → OB1_PREV_CYCLE and OB1_MIN_CYCLE. Target ≤ 50% of OB 30 period to leave scheduler headroom.
2. Connect each PID block to a time-of-day / cyclic interrupt OB. Do not call FB 41 from OB 1 except in bench tests.
3. Configure SM 431 integration time to 60 Hz or 50 Hz noise rejection unless your plant noise is white; faster conversion rates increase A/D noise and increase derivative chatter.
4. Enable the controller's bumpless transfer (BMP_ON = TRUE for CONT_C; "Output ramp" parameter on PID_Compact).
5. Record T_s, Kp, Ti, Td for each loop in the Loop Documentation report. Required by ISA-88 / IEC 61511 change management.
6. Run the loop in manual for 1×τ and check that the plant moves in the expected direction before any auto mode trial.
7. Inject a 10% set-point step and tune Ti first, then Kp, then Td. Confirm overshoot < 10% and IAE meets the loop's performance specification.

Verification: Quantifying "Better" PID Performance

"Better" is a measurable property. Use the following metrics during commissioning and record them in the FDS / SAT:

• IAE — Integral of Absolute Error: IAE = ∫ |e(t)| dt over a 10-min setpoint step test.
• ITAE — Integral of Time-multiplied Absolute Error, penalizes long settling: ITAE = ∫ t · |e(t)| dt.
• Loop dead time L and dominant time constant T from a step response.
• Standard deviation of MV at steady state — measures controller noise immunity.

A correctly tuned S7-400 loop and a correctly tuned S7-1200 loop on the same plant will give IAE values within 5% of each other. The platform contribution shows up under disturbance rejection and setpoint tracking under load swings, where the S7-400's deterministic scheduler and faster analog I/O yield lower standard deviation in the MV. If your acceptance criterion is tight (e.g., IAE < 1.2% of setpoint at 6 s after a 10% load step), the S7-400 family is the engineering-correct choice; if the criterion is loose (e.g., IAE < 5% at 60 s), the S7-1200 will pass.

Field-Proven Caveats

FAQ