Siemens CPU31xC High Speed Counter Architecture and Configuration

Overview of Integrated Counting on S7-300 Compact CPUs

The SIMATIC S7-300 Compact CPUs (CPU 312C, CPU 313C, CPU 313C-2 DP/PtP, and CPU 314C-2 DP/PtP) integrate technological functions directly on the module. These include high-speed counters, frequency measurement, and pulse-width modulation. Unlike standard digital inputs that are evaluated by the cyclic process image update, the integrated counter channels of the CPU 31xC are evaluated by a dedicated hardware block on the module and can therefore detect pulse edges that are far shorter than the OB1 cycle time of the CPU.

The reference document for these functions is the SIMATIC S7-300 Technology Functions manual (order number 6ES7390-1AF30-0AA0 / file S7300C_tf_e.pdf), Chapter 5. The hardware description and wiring details are covered in the S7-300 CPU 31xC and CPU 31x Manual (file HB_CPU31xC_und_CPU31x_e.pdf). The application of the counting function for general SIMATIC S7 CPUs is described in the Counting Function Manual (file GS_ZAEHLEN_E.PDF).

Why Counting Works Despite Slow OB1 Cycle

OB1 executes the user program cyclically. The cycle time of a CPU 314C with a fully loaded program is typically between 5 ms and 20 ms. A pulse train from a 10 kHz incremental encoder has a period of 100 µs - two orders of magnitude shorter than the OB1 cycle. Yet the CPU 31xC counts every pulse correctly. Three architectural details make this possible:

1. Dedicated counter hardware on the compact CPU: The integrated counter channels are implemented in a hardware block (ASIC + counter register) that is clocked independently of the CPU's scan cycle. Each incoming pulse is latched into a 32-bit hardware counter register on the rising edge of the pulse.
2. Direct hardware-to-memory mapping: The hardware counter value is mapped into a fixed address range in the I/O area of the CPU. The application can read this value at any time without first having to request it from the technology module.
3. Hardware interrupt on comparator events: If the count value reaches a configured comparison value, a hardware interrupt (OB 40) can be triggered, bypassing OB1. The interrupt latency is in the microsecond range, not the cycle range.

The technology functions are therefore not executed in the OB1 cycle. They run in the background. The OB1 cycle only serves to coordinate the data exchange between the user program and the technology module via special system function blocks (SFBs). The SFBs do not start or stop the counter - the counter runs continuously as soon as it has been parameterized and enabled.

CPU 31xC Model Variants and Counter Performance

The number, maximum frequency, and operating modes of the integrated counter channels depend on the specific compact CPU in use. The following table summarizes the counter capabilities of the relevant CPU 31xC variants. Values are taken from the CPU 31xC Manual Collection and the S7-300 Module Data Manual.

Supported Counting Modes

Each counter channel can be operated in one of three counting modes, configured via HW Config under the properties of the CPU in STEP 7. The same channel cannot be switched at runtime - the mode is fixed at configuration time.

The CPU 314C-2 also supports the A/B counter mode (SFB 38), which uses two pulse trains in quadrature (phase-shifted by 90°). The hardware decodes the direction of rotation and increments or decrements the count value accordingly. Multiplication by 4 (counting every edge of both channels) is also selectable. The maximum input frequency in A/B mode is reduced by a factor of 4 compared to single-channel counting (15 kHz on CPU 314C-2).

Hardware Wiring and Encoder Interface

The integrated counter inputs are located on the front connector X1 of the CPU. Pin-out (CPU 314C-2 example):

Encoder wiring notes:

• Use shielded twisted-pair cable for all encoder signals. Connect the shield to the grounded S7-300 mounting rail at both ends (low-impedance).
• Provide a separate 24 V supply for the encoder. Do not power the encoder from the CPU's 1L+ terminal if the encoder current exceeds 200 mA - use an external power supply.
• The hardware gate input must be tied to a defined level (24 V for "gate open", 0 V for "gate closed") if the hardware gate is not used. The CPU will not count without a defined gate level.
• Maximum cable length: 50 m for 24 V encoders at 10 kHz. For higher frequencies or longer runs, use encoders with line-driver outputs and an external signal converter.

Configuration in STEP 7 HW Config

The integrated technology is configured in HW Config in STEP 7 V5.x (the configuration tool for S7-300). The steps are:

1. Open the SIMATIC 300 station and select the CPU 31xC.
2. Double-click the CPU to open the properties dialog. Switch to the "Counting" tab.
3. Activate the channels you want to use (Channel 0, Channel 1, ...).
4. Select the counting mode (Endless, Periodic, or Frequency) and the operating mode (single-phase, two-phase with direction, A/B quadrature).
5. Set the maximum count value (only relevant for periodic counting).
6. Configure the hardware gate behavior (cancels count, interrupts, no effect).
7. Assign the hardware interrupt (OB 40) sources if comparator events are needed.
8. Set the input filter time (0.5 µs, 1 µs, 2 µs, 5 µs, 10 µs, 20 µs). The filter suppresses noise but reduces the maximum count frequency. For 60 kHz counting, use 2 µs or smaller.
9. Compile and download the hardware configuration.

System Function Blocks for Counting

Once the channel is configured, the application exchanges data with the technology module through the SFBs listed below. The SFBs are part of the SIMATIC library and are called from OB1 or any other user program block.

Each SFB instance is a system data block (DB) that must be assigned a number. The instance DB holds the channel parameters, the current count, the status bits, and the comparison values. A separate instance DB is required per channel.

Programming Example: SFB 29 in Endless Counter Mode

The following STL snippet shows the minimal call sequence for an endless counter with a comparator. The comparator triggers a hardware interrupt (OB 40) when the count reaches the comparison value.

// Call SFB 29 for channel 0
// Instance DB: DB 30 (assigned in HW Config or inserted manually)
CALL SFB 29, DB 30
  LADDR   := W#16#100          // Logical address of channel 0 (configurable)
  CHANNEL := 0                 // Channel number on the CPU
  SW_GATE := I0.0              // Software gate - 1 = counting enabled
  CTRL_DO :=                   // Direct control of digital output (optional)
  SET_DO  :=                   // Set DO on comparator event
  JOB_REQ :=                   // 1 = execute a job (e.g. set count)
  JOB_ID  :=                   // Job identifier
  JOB_VAL :=                   // Job value
  STS_GATE:  =                 // 1 = gate open
  STS_STRT:  =                 // 1 = counter has been started
  STS_LTCH:  =                 // Latch bit - comparator reached
  STS_DONE:  =                 // Job complete
  STS_C_DN:  =                 // Count downward active
  STS_C_UP:  =                 // Count upward active
  COUNTVAL:  MD100             // Current count value (DINT)
  MEASVAL:                      // Measured frequency (DINT, in 0.1 Hz)

The hardware configuration in HW Config assigns the logical base address W#16#100 for channel 0 by default. The address is shown in the properties dialog of the CPU under the tab "Addresses". The instance DB must be created with the same number that is referenced in HW Config ("Counting" tab, "Instance DB for SFB 29").

Hardware Interrupt (OB 40) and Comparator Events

Each counter channel has two comparison values. When the count value crosses a comparison value (either upward or downward), the CPU can trigger a hardware interrupt OB 40 if this is configured in HW Config. The OB 40 contains the event identifier in the local data at OB40_POINT_ADDR (16 bits) and the channel number. The interrupt latency is in the order of 100-300 µs, which is sufficient for fast reaction on a count event without requiring OB1 polling.

Typical OB 40 implementation for a comparator event:

ORGANIZATION_BLOCK OB 40
TITLE = "Hardware Interrupt - Counter Event"
VAR_TEMP
  OB40_EV_CLASS : BYTE;    // 16 = interrupt activated
  OB40_STRT_INF : BYTE;    // 2 = OB was entered
  OB40_POINT_AD : DWORD;   // Address of event source
  OB40_FLT_ID   : BYTE;    // Fault identifier
  info          : ARRAY[1..20] OF BYTE;
END_VAR
BEGIN
  // Read event source: low byte = channel, high byte = event type
  L     #OB40_POINT_AD;
  L     DW#16#0000FFFF;
  AW;
  T     MB 200;            // MB 200 = channel number that caused the interrupt
  // Custom reaction code:
  SET   ;
  S     M 101.0;           // Set "comparator reached" flag for OB1
END_ORGANIZATION_BLOCK

Data Consistency and the Snapshot Mechanism

Because the counter value changes asynchronously to OB1, reading the count value during a long OB1 scan can result in an inconsistent value being read (e.g., a value that changes between the high word and the low word read). To prevent this, the CPU 31xC provides a snapshot mechanism: a dedicated I/O read operation on the counter channel's logical address latches the current 32-bit count value into an internal buffer, and the subsequent read of the two 16-bit words returns the latched value. The SFB 29 internally performs the snapshot read, so applications that use SFB 29 do not need to handle this manually.

Comparison with S7-1200 High-Speed Counters

The S7-1200 family also provides integrated high-speed counters, but the architecture and configuration approach differ significantly from the CPU 31xC. The S7-1200 supports up to 6 high-speed counters on the CPU 1214C (CPU 1212C: 4, CPU 1211C: 3) with maximum frequencies of 100 kHz single-phase and 80 kHz in A/B mode. The HSC is configured in TIA Portal through a dedicated HSC configuration dialog, and the counting is controlled by the CTRL_HSC instruction in the program.

Key differences:

For projects migrating from CPU 31xC to S7-1200, the SFB 29 logic can be rewritten as a CTRL_HSC call. The HSC IDB of the S7-1200 contains the current count value at the COUNT symbol. Detailed configuration is documented at Configuring a high-speed counter on TIA Siemens Documentation and the general overview is provided at General information on high-speed counters (S7-1200) in the Siemens Industry Online Support.

Commissioning Checklist

1. Verify that the CPU 31xC firmware version supports the desired counting mode. CPU 314C-2 with firmware V2.0 or higher is required for the A/B counter (SFB 38).
2. In HW Config, set the input filter to a value appropriate for the maximum expected frequency. For 30 kHz: filter ≤ 2 µs. For 60 kHz: filter ≤ 1 µs.
3. Connect the encoder supply and the signal lines. Tie the hardware gate input to a defined level (24 V for "gate open") if the hardware gate is not used.
4. Download the hardware configuration. Verify in the CPU diagnostic buffer that no configuration errors are reported (event ID 16#4931, 16#4932).
5. Insert the instance DB for the SFB 29 / SFB 30 / SFB 38 in the S7 program.
6. Call the SFB in OB1 and set SW_GATE = TRUE.
7. Force the count value via the SFB 29 JOB interface (JOB_ID = 1) to test the system before connecting the live encoder.
8. Connect the encoder, run a slow-speed test, and verify the count increments in the VAT (Variable Table) when monitoring the instance DB.
9. Verify the hardware interrupt path by setting a comparison value below the current count and confirming that OB 40 is entered.

Troubleshooting Matrix

Field-Proven Tips and Caveats

• The SFB 29 must be called in OB1 (or a higher-priority OB) at least once per cycle. Even if the application only wants to read the count value, the SFB must be called so that the instance DB is updated.
• The instance DB of SFB 29 / SFB 30 must be marked as non-optimized (classic DB) if the application reads its symbols from external sources. The S7-300 classic DBs do not support optimized block access.
• For A/B counting with a 24 V single-ended encoder, the phase shift of 90° must be guaranteed over the full frequency range. Open-collector encoders with slow rise times may not produce a clean 90° shift above 10 kHz. Use push-pull (PNP) encoders for A/B mode above 20 kHz.
• The maximum count frequency in the data sheet is a hardware limit. It assumes a 50% duty cycle. If the encoder produces short pulses (low duty cycle), the maximum usable frequency is lower because the input filter rejects pulses shorter than the filter time.
• Do not use the integrated DO of the CPU 31xC for switching inductive loads without external free-wheeling protection. The DO is rated 0.5 A but the internal protection is not designed for repetitive switching of contactors or solenoids.
• For applications requiring more than 4 counters, use the FM 350-1 or FM 350-2 counter modules in the S7-300 rack. These provide 1-8 counter channels with higher accuracy and additional functions such as measurement mode.