Siemens LOGO! Shift Register: Fix M8 Double-Trigger at Startup

When the automatic shift register example in LOGO!Soft Comfort (LSC) is used to cycle through message texts, adding the marker M8 as a startup trigger causes the shift register to advance two positions at once. The same logic also exhibits retentivity lock-up (a bit stays 1 if reset is asserted while the register is high) and message texts disappear after three to four power cycles in simulation. This article walks through the root cause of the M8 double-trigger, explains what shift register index and shift register bit actually mean in the LSC output connector, and provides field-proven fixes for retentivity, power-on initialization, and the disappearing message-text symptom.

1. Problem Summary

2. How a Shift Register Works (Foundation)

A shift register is a cascade of flip-flops where the output of stage n feeds the input of stage n+1. On each clock edge, every bit moves one position to the right (or left, depending on direction) and a new bit is accepted at the input. A cascade of N flip-flops therefore holds an N-bit word, and after N clocks the original value has fully shifted out.

• Source: Shift register — Wikipedia
• Reference hardware: Shift registers — Texas Instruments

The conceptual model is identical inside LSC. The shift register block in a LOGO! program stores up to 8 bits (stages). Each clock on the trigger (Trg) input shifts the bits one position; the Set (S) input writes a 1 into the first stage, the Reset (R) input clears every stage to 0.

3. Root Cause: Why M8 Triggers Two Bits

The LSC simulation engine treats the rising edge of the simulation start as one clock event, and the marker M8 — if it is forced to 1 via a startup pulse or by being wired to a power-on condition — produces a second rising edge in the same scan. The shift register, which is edge-triggered on the Trg input, sees two edges and advances the cascade by two positions in a single cycle.

Concretely:

1. Scan 1, t=0: simulation starts, register is empty (0000 0000).
2. Scan 1, t=0+: M8 evaluates 1 and the power-on pulse generator fires simultaneously. Both rising edges arrive at the Trg input of the shift register block.
3. Scan 1, t=0++: register becomes 11 00000 — two bits set, not one.

This is the exact symptom reported: "Shift register identifies two signals so it activates two bits at the same time." It is not a bug in the shift register; it is the expected behaviour of an edge-triggered block fed by two simultaneous edges.

3.1 Edge detection vs. level detection

The shift register's Trg input is edge-triggered, not level-triggered. A level that is simply held 1 will not advance the register — only the transition from 0 to 1 does. If the simulation start and the M8 output both transition from 0 to 1 on the same scan, the block counts two transitions.

4. The Output Connector: Index vs. Bit

The "output connector" of the shift register block exposes two selectors that are easy to mix up:

Plain-English explanation. Imagine a row of eight mailboxes, numbered 1 to 8 from left to right. Each time a clock arrives, every letter moves one mailbox to the right and a new letter drops into mailbox 1.

• The shift register index is "the mailbox that the postman is currently standing in front of." You can move the postman (1 to N) and whatever is in that mailbox at the moment is what you get.
• The shift register bit is "the contents of mailbox 5, right now, regardless of where the postman is."

For cycling message texts, you typically want the shift register bit output, selecting bit 1, bit 2, … bit N as discrete outputs and using those to enable individual text blocks. The index is rarely used in message-text sequencing; it is more useful when you want to read out the register in a fixed order without wiring every bit to a coil.

5. Solution 1 — Eliminate the Double-Trigger on M8

Three fixes are available, in order of preference:

5.1 Use a one-shot (edge) on the M8 path

Insert an edge-triggered pulse generator between M8 and the Trg input. The pulse generator converts the steady 1 from M8 into a single, scan-bounded 1. Combined with the simulation-start edge, this still produces two edges — but if the simulation-start edge is replaced by a software initialisation (see 5.3), only one edge remains.

5.2 AND the M8 with a NOT(startup pulse)

Generate a one-scan power-on pulse using a special marker (see the LOGO! documentation for the available startup flags) and invert it. AND the result with M8 before feeding Trg. This masks the first scan, when the simulation-start edge and M8 would otherwise co-fire.

5.3 Pre-load the register with Set, then clock

Use the Set (S) input of the shift register to write a 1 into bit 1 on power-up, and use the Trg input only for subsequent clocks. Because S sets bit 1 directly (it does not edge-trigger), the simultaneous edges on Trg are harmless: bit 1 is already 1, and the first real clock moves it to bit 2. The message text associated with bit 1 is then guaranteed to display at startup, which is the original intent of adding M8.

             +--------+
   M8 ------>|        |
             |  AND   |------+--- Trg (Shift Register)
  /P_on ---->|        |
             +--------+

  /P_on = inverted power-on flag (high after first scan)
  M8    = user-defined marker for the start condition

6. Solution 2 — Retentivity Lock-Up

The reported symptom: "If you reset it while the register is at high, it stays high, thus injecting another high."

This is the documented behaviour of a retentive shift register. When retentivity is enabled, the on/off state of each bit is stored in non-volatile memory. If the Reset (R) input is asserted while a bit is 1, the volatile part of the register is cleared — but the retentive backup is not, and on the next scan the backed-up value is reloaded, so the bit appears to "stay high." If a Set is then issued, the register reads as having two 1s.

6.1 Fix

1. Open the shift register block properties in LSC.
2. Locate the Retentivity checkbox and disable it for the shift register while you are debugging the double-trigger problem.
3. Run the simulation. The bit will now clear cleanly when R is asserted.
4. Once the logic is correct, re-enable retentivity if the application requires that the sequence survive a power cycle.

7. Solution 3 — Active Bits at Startup

The manual's example shows a shift register that has bit 1 already 1 at startup. To replicate this in your own program:

1. Place the shift register block.
2. Configure it for the number of stages you need (1-8).
3. Wire the Set (S) input to a power-on pulse (a one-scan-high marker generated from a special startup flag or a self-latching coil cleared by a TOF timer).
4. Wire your real clock source (button, sensor, etc.) to Trg.
5. Wire Reset (R) to whatever condition should clear the sequence.

The Set input is level-sensitive, not edge-sensitive, so holding it for one scan writes exactly one 1 into bit 1. This is the cleanest way to get a single active bit at startup without using M8 at all.

8. Solution 4 — Messages Disappearing After Power Resets

The reported symptom: text messages stop working after three or four power resets in simulation.

Three likely causes, in order of probability:

9. Solution 5 — Hardware Does Not Start After Power-Fail Simulation

The reported symptom: "the hardware does not start automatically after a power failure." This is normal LOGO! behaviour, not a bug:

• On a real LOGO! module, the outputs are de-energised during a power dip and re-energised only after the RUN/STOP switch (or the configured power-on mode) allows it.
• Many LSC simulation "power-fail" buttons stop the simulation engine and require an explicit RUN command to resume.
• If the program depends on a power-on pulse to initialise state, and that pulse is generated by a retentive marker that was forced 0 by the simulation stop, the program will indeed appear dead after a simulated power-fail.

To make a simulated power-fail recoverable, ensure the program has a true power-on initialisation path that is independent of retained state. The classic pattern is a TOF (off-delay) timer with a long time constant driven by a real input; on cold start, the TOF output is 1 for one period, providing the initialisation pulse.

10. Recommended Program Architecture

Based on the failures above, the recommended LSC program structure for "cycle through N message texts on demand" is:

1. One power-on pulse generator — produces a single-scan 1 on cold start.
2. Shift register block, retentivity OFF during development — 1 to 8 stages.
3. Set input wired to the power-on pulse — guarantees bit 1 is 1 at startup.
4. Trg input wired to the user event (button, sensor, etc.) — one event = one clock = one bit advance.
5. Reset input wired to the user reset condition OR to a TOF timeout — clears the register when the sequence completes.
6. One message text block per shift register bit — En input wired to the corresponding bit output of the shift register.
7. No M8 in the clock path — M8 (or any marker) is fine as a status indicator, but should not feed Trg directly.

11. Verification Checklist

After applying the fixes, confirm each item:

12. Frequently Asked Questions