Siemens MasterDrive F026 UCE Fault: Troubleshooting Phase L2

1. Overview

The Siemens SIMOVERT Master Drive family (now integrated under the SINAMICS platform lineage, with the 6SE70 series as the canonical MasterDrive hardware) generates a structured set of UCE faults that localize IGBT desaturation events to a specific output phase. Fault F026 reports a UCE (Collector-Emitter saturation voltage) shutdown on Phase L2, which on the standard U-V-W terminal mapping of a MasterDrive corresponds to the V-phase leg of the inverter bridge. Because F026 is a hardware-level shutdown with potential for catastrophic power-stage damage, it must be diagnosed with the drive disconnected from the line, the DC bus fully discharged, and the unit locked out per local safety procedure.

The MasterDrive implements phase-specific UCE monitoring rather than a single combined fault for two reasons:

1. It pinpoints which IGBT half-bridge saturated (upper or lower of U, V, W), reducing mean-time-to-repair on multi-MW drives.
2. It distinguishes genuine desaturation from cross-talk induced false trips on long-gate-drive cables in larger chassis (≥ 250 kW).

2. Fault Code Definitions and Phase Mapping

The MasterDrive fault numbering groups the three phase-specific UCE events into a contiguous block. Confirm the fault number on the PMU (Parameterization Unit) or OP1S operator panel before opening the drive, because the corrective action differs by phase.

If the drive also reports F025/F026/F027 simultaneously, this is generally an IVI (Inverter Interface) board failure, not three independent IGBT failures. A single isolated F026 points to the L2 leg specifically.

3. UCE Detection Principle

UCE monitoring is a desaturation protection method. Each IGBT gate-driver card contains a comparator circuit that monitors the collector-emitter voltage (V_CE) of the IGBT while it is commanded ON. Under normal operation, a saturated IGBT has V_CE(sat) in the range of 1.8 V to 3.2 V depending on collector current and junction temperature. The detection threshold on MasterDrive IGD boards is typically set around 7 V to 10 V; if V_CE exceeds this threshold while the gate is commanded ON, the comparator trips.

The trip event does two things inside the IGD card:

1. It removes the gate drive signal within microseconds, hard-turning-off the IGBT.
2. It pulls the corresponding optical fiber LOW, signaling the IVI board via the FO link that a UCE event occurred in that phase.

The IVI board registers the optical signal and forwards the fault to the CU (Control Unit) over the backplane. The CU then raises F025, F026, or F027 and executes the configured fault response (typically OFF2 — ramp to zero then pulse inhibit).

4. MasterDrive Architecture for the L2 Leg

The signal and power path for Phase L2 runs from the CU down through several distinct layers. Diagnosticians must understand which layer failed before swapping parts.

5. Diagnostic Decision Tree

Apply the following sequence before concluding that the IGD board is faulty. Skipping steps is the most common reason technicians replace good parts.

1. Capture the fault buffer. Read r947 (fault number) and r949 (fault time) on the PMU. Note whether F026 appears alone or alongside F025/F027.
2. Visual inspection with the drive de-energized. Look for discolored gate resistors, cracked PCB on the L2 IGD, blown MOV, or evidence of arcing on the V-phase IGBT.
3. Inspect all fiber optic links. Check both the transmitter and receiver ends; verify the FO cables are not kinked, pinched, or pulled beyond their minimum bend radius. A dirty FO end-face attenuates the signal and produces spurious UCE trips.
4. Clean or replace the FO cables if contamination is suspected. Use a proper FO cleaning pen (e.g., Cletop SFB-250) rather than a wipe.
5. Swap the IGD board for the L2 slot with a known-good spare. Power up and run a no-motor test (motor disconnected, run enable, low frequency reference) to confirm whether the fault follows the board.
6. If the fault follows the board → IGD card is defective. Replace.
7. If the fault stays on the L2 phase → proceed to IGBT, CT, and IVI testing.

6. Fiber Optic Link Verification

Fiber optic cables transmit both the gate-on command (light ON = drive IGBT) and the UCE status (light OFF or pulsing = fault) between the IVI and each IGD. On MasterDrive units, each phase uses two FO links: one for upper IGBT and one for lower IGBT of that phase leg.

Verification procedure:

1. With the drive powered but in pulse inhibit (no run command), use an FO tester or a photo diode probe to verify each link.
2. On a healthy system with no faults and DC bus charged, you should observe a steady low-frequency PWM pattern on the FO scope trace when the drive is enabled without run command (gate pulses visible at low duty).
3. If the FO link for the L2 lower IGBT is dim or dead, the UCE comparator on the IGD has likely tripped and latched — and the IGD may be reporting a UCE even when no actual desaturation occurred.
4. Replace the FO cable set if any link fails the light-level check. Re-test.

7. IGD Board Replacement (Phase L2)

If the FO links test good and the fault follows the swapped card, the IGD board in the L2 position is defective. Replace as follows:

1. Lock out and tag out the drive. Wait the prescribed discharge time. Verify DC bus < 50 V.
2. Remove the FO cables from the L2 IGD.
3. Remove the gate wires (typically a 2-pin or 4-pin connector) from the IGD to the upper and lower V-phase IGBTs.
4. Unplug any auxiliary feedback connector (DC-link voltage sense for that phase).
5. Release the card retention screws or latches and remove the IGD card.
6. Install the replacement IGD card in the same slot.
7. Reconnect gate wires (observe polarity — the red-stripe or keyed connector is non-reversible).
8. Reconnect FO cables — verify they click into place; a half-insertion produces intermittent F026.
9. Apply control power only (no main power). Verify the PMU shows no fault and the FO test points toggle as expected.
10. Apply main power, run a no-motor test, then a motor test at no-load low speed before returning to service.

For 6SE70 series MasterDrives, IGD part numbers follow the pattern 6SE7090-0XX84-... variants. Confirm the exact order number against the drive's device plate (MLFB) before ordering.

8. IGBT Module Testing (V-Phase)

If the IGD board swap did not resolve F026, the V-phase IGBT module is the next suspect. Field technicians most often diagnose this by measuring the module while de-energized.

8.1 Static Test Procedure

1. Disconnect the gate leads from the IGD to the V-phase IGBT module.
2. Using a digital multimeter on diode-test mode, measure between collector and emitter for each of the upper and lower IGBTs in the V-phase leg.
3. A healthy module shows approximately 0.3 V to 0.7 V in the forward direction and open-circuit (OL) in the reverse direction for each individual IGBT body diode.
4. A shorted module reads near 0 V in both directions.
5. An open module reads OL in both directions.

8.2 Resistance Reference for Compact-Type CTs

The current transformer used on the V-phase output is a "compact type" with documented winding resistance. Use these values as a sanity check when measuring the secondary winding with the meter disconnected from the IVI board:

A reading substantially different from 23.9 Ω or 53.5 Ω indicates a CT winding fault or an open / shorted burden resistor on the IVI board input stage.

9. IVI Board Considerations

The Inverter Voltage Interface board is the central signal routing for all six IGBT gate commands and all six UCE fault returns. It is uncommon for the IVI to fail in isolation on a single phase. However, when an IGBT failure has caused a high-energy event, the IVI's input protection network can be damaged. If F026 persists after replacing both the IGD and the IGBT module, suspect the IVI board.

Recommended verification:

1. Measure the IVI input optocoupler LED forward voltage for the L2 phase FO receiver. A healthy receiver reads about 1.2 V to 1.5 V when illuminated.
2. Check for burned components around the L2 input stage on the IVI board.
3. If the IVI is replaced, ensure all firmware / parameter compatibility (parameter set) is reloaded before commissioning.

10. Current Circuit and CT Path

The UCE monitor and the closed-loop current controller both rely on the V-phase CT secondary. If the CT burden is open or shorted, the controller may command abnormally high di/dt into a partially-de-saturated IGBT and produce a genuine (but secondary) UCE trip.

Checklist for the current path on Phase V:

• CT secondary wiring intact, no broken strands at the terminal block.
• Burden resistor on the IVI input is correct value (typically 33 Ω to 100 Ω depending on CT type).
• CT polarity: the dotted terminal must face the inverter side. Reversed polarity does not cause F026 directly but produces erratic current regulation and can trigger secondary trips.
• Compare the V-phase current reading in r074 (or the equivalent) against U-phase and W-phase at the same load. A V-phase reading outside ±5 % of the average of U and W points to a CT or burden problem.

11. Verification After Repair

Once the suspected component has been replaced, run the following verification sequence before returning the drive to production:

1. Insulation test. Megger the motor and cabling at 500 V or 1000 V per the motor spec.
2. No-motor run. With the motor leads disconnected, enable the drive, ramp to 5 Hz, observe current draw. All three phases should read < 5 % of rated current (only magnetizing current of the output filter / cable capacitance).
3. No-load motor run. Connect motor, decouple load, ramp to rated frequency, monitor r074 / r075 / r076 for symmetry. Temperature-rise check on the replaced IGBT heatsink for 30 minutes.
4. Loaded run. Re-couple the load, run through the normal duty cycle. Confirm no F026 reoccurs across at least one full thermal cycle.
5. Fault buffer clear. Acknowledge the fault (r949 clear) and confirm r947 = 0 before handing the drive back to operations.

12. Preventive Maintenance for Recurrence Prevention

UCE faults on MasterDrive are often preceded by environmental or maintenance root causes that, if uncorrected, will damage the replacement parts as well. Address the following:

• Cooling. Verify heatsink fin integrity and fan operation. The L2 IGBT heatsink temperature is reported via the IGD card's onboard thermistor and should not exceed 95 °C at full load.
• Contamination. Dust, oil mist, and conductive debris on FO end-faces and PCBs are a leading cause of intermittent UCE trips. Schedule quarterly cleaning in dirty environments.
• Gate-driver supply. Verify the +24 V and +15 V supplies feeding the IGD cards are within ±5 % under load. A sagging +15 V rail can cause insufficient gate drive and partial turn-on of the IGBT, leading to desaturation under load.
• DC bus capacitance. Aging DC bus capacitors increase ripple, which stresses IGBTs at the switching edges. If the drive is > 10 years old and DC bus ripple exceeds 5 %, schedule capacitor replacement.
• Documentation. Log every F026 event with timestamp, load condition, ambient temperature, and the component replaced. Patterns in the log identify the actual root cause faster than any single repair.

13. Troubleshooting Matrix

14. When to Escalate

Escalate to a Siemens-authorized service partner or to Siemens Technical Support when:

• F026 recurs within the warranty period of a newly installed IGD card.
• The drive is part of a coordinated multi-drive system (master-follower, load sharing) and F026 on one unit may indicate a system-level issue such as harmonic resonance.
• Multiple phases have failed simultaneously or in close succession.
• The drive is in a Safety Integrity Level (SIL) application and the root cause must be documented for functional-safety compliance.

Always reference the drive's MLFB (machine-readable product designation) and the firmware version of the CU (read from r060 or equivalent) when contacting support.

15. Frequently Asked Questions