Siemens S7-1200 High-Speed Counter HSC Configuration on TIA

Overview

The Siemens SIMATIC S7-1200 CPU family integrates a hardware-based high-speed counter (HSC) capable of evaluating pulse trains well beyond the scan cycle of the OB1 program. Built-in HSC channels on the CPU can decode single-phase, two-phase directional, and AB quadrature encoder inputs at up to 100 kHz on a CPU 1211C, and up to 200 kHz on CPUs 1212C, 1214C, 1215C, and 1217C, plus on the optional signal boards (SB) that plug into the top of the CPU. Applications that routinely reach for HSC functionality include flow metering, length measurement, parts-per-minute counting, web tension feedback, and incremental-encoder position loops on small servo and stepper systems.

The goal of this reference is to walk a control engineer through the practical commissioning of an S7-1200 HSC: from choosing the correct CPU and signal board, to wiring the encoder, to configuring the HSC in TIA Portal V16 or later, to writing compact logic that reads, presets, and gates the counter. A dedicated section addresses why the S7-PLCSIM and PLCSIM Advanced simulators will not exercise HSC, and a troubleshooting matrix is included for the most common field issues. The reference closes with a side-by-side comparison of HSC implementations on the S7-1200, an Allen-Bradley ControlLogix 1756 module, and a CTI 2500-Series module so the engineer can match the architecture to the application.

Prerequisites

• SIMATIC S7-1200 CPU, firmware V4.4 or later (V4.5 recommended for full TIA Portal V17 support). Verify the firmware under Online & Diagnostics → Diagnostics → CPU Information.
• STEP 7 / TIA Portal V16 SP1 or later. TIA Portal V18 is the current engineering baseline; V19 is the latest release stream and adds the unified HSC commissioning wizard.
• 24 V DC control power, fused at 1 A minimum, and a clean PE bonding path to the encoder cable shield.
• Incremental encoder or pulse source. For 24 V push-pull, use a Siemens SIMATIC S7-1200 digital input or the SB 1221 DI signal board. For 5 V differential (RS-422), use the SB 1221 DI with the differential option, or a Siemens SSI/HSC signal board.
• Physical CPU on the lab bench. Do not attempt HSC commissioning on S7-PLCSIM; the simulator does not toggle HSC inputs at the required edge rate, and the HSC control bits and the IDB instance fields remain frozen.
• The S7-1200 System Manual, edition 06/2021 or later, available from the Siemens Industry Online Support portal.

S7-1200 HSC Architecture

The S7-1200 HSC is implemented in the CPU firmware as a dedicated hardware block. Up to six HSC channels are exposed, but the number available depends on the CPU variant and the installed signal boards. Each HSC has a fixed pin assignment that maps to the on-board digital inputs of the CPU (I0.0 to I1.3 in most cases) and to the optional digital inputs on the SB 1221 board. The HSC does not consume OB1 scan time; the count is latched on every input edge and a new process image is available in the Instance Data Block (IDB) of the HSC.

CPU HSC Count Specifications

HSC Operating Modes

Why S7-PLCSIM Does Not Drive HSC

Both S7-PLCSIM (legacy) and PLCSIM Advanced (virtual PLC) faithfully simulate the bit-logic and most of the user-level instruction set of the S7-1200, but high-speed edge-sensitive peripherals are explicitly out of scope. The PLCSIM documentation states that technology objects with hard real-time requirements (HSC, PTO, PWM, SSI, motion) are not modeled with deterministic timing. The S7-1200 HSC latches its count on the physical input pin; in the simulator the input pin can only be forced manually, and the input filter on the HSC is enforced at the simulated scan rate rather than at the encoder's edge rate.

Wiring the Encoder to the S7-1200

24 V Push-Pull Encoder (Most Common)

1. Connect the encoder's 24 V supply to the CPU's 24 V sensor power terminal (terminal M is the 0 V return).
2. Wire channel A to the HSC's default clock input. For HSC1, this is I0.0 on the CPU body. For HSC2, I0.1. The mapping is fixed by hardware and is documented in the S7-1200 System Manual, section 6.3.
3. Wire channel B to the direction or quadrature input. For HSC1 quadrature this is I0.1. For HSC1 single-phase external direction, the direction input is I0.3.
4. For Z (index) input, wire to I0.2 for HSC1, I0.4 for HSC2.
5. Bond the encoder cable shield at the cabinet entry using a 360° EMC gland, and tie PE to the cabinet ground bar at one point only.

5 V Differential (RS-422) Encoder

For high-frequency encoders (>100 kHz) or for long cable runs where noise immunity matters, use the SB 1221 DI signal board (order number 6ES7221-3AD30-0XB0 for the 5 V / 24 V DI 4x variant) wired for differential input. The signal board's pins are mapped to HSC inputs 1-3 by default when the SB is plugged in. The differential receiver in the SB provides hysteresis and common-mode rejection, which is critical for the 200 kHz edge rate.

Configuring HSC in TIA Portal

1. In the project tree, expand PLC_1 → Technology Objects → Add new object. Choose High_Speed_Counter and click OK.
2. In the configuration wizard:
   • Select the HSC number (HSC1 through HSC6).
   • Assign a symbolic name (e.g., EncoderPosition). The wizard creates an FB and an Instance DB.
   • Select the count mode (e.g., Counting and measuring → Quadruple (A, B, Z)).
   • Assign the input pin group. For the on-board HSC1, the defaults are I0.0 (A), I0.1 (B), I0.2 (Z).
3. Set the initial count value, the upper limit, and the lower limit. The upper and lower limits are used by the HSC's hardware compare logic. A typical range for a 24-bit signed counter is −2,147,483,648 to +2,147,483,647.
4. Configure the gate input (e.g., I0.6). The gate is an enable: when the gate is high, the HSC counts; when the gate is low, the count is held.
5. Configure the event detection. The HSC supports a high limit reached, low limit reached, and a digital input level change. Each event can trigger an OB and/or set a status bit in the IDB.
6. Download the project to the CPU. Important: open the configuration window and click Restart HSC after the first download so the new parameters take effect on a stopped CPU.

Programming the HSC

The HSC exposes its current value, status, and control bits in the instance DB. The current value is read with a simple MOVE, but the control interface is more nuanced. The following examples assume HSC1 is named HSC_1_Encoder.

Ladder Logic: Preset on Z-Pulse

// Reset counter on Z-pulse + machine home signal
A     "Z_Pulse_OK"        // Z index from HSC1
A     "Machine_Home_OK"   // Operator home request
FP    "Home_Edge"         // Edge memory bit
JCN   END

L     0
T     "HSC_1_Encoder".PresetValue

CALL "CTRL_HSC_EXT"
  HSC     := 1
  CTRL    := 16#F0        // Load preset, enable count, no direction change
  PRESET  := 0
  NEW_DIR := FALSE
END: NOP 0

SCL: Period Measurement

// Period measurement using HSC input edge timing
#Period_Start := #HSC_1_Encoder.CurrentValue;
IF #Gate_OK AND #Period_Start > #LastValue THEN
    #Period_us := DWORD_TO_UDINT(#Period_Start - #LastValue);
    #Frequency_Hz := UDINT_TO_REAL(1_000_000) / UDINT_TO_REAL(#Period_us);
END_IF;
#LastValue := #Period_Start;

Reset and Gate Control from HMI

Wire two HMI tags to the IDB. Status_Counting (BOOL) is the high-level count enable and is mapped to the IDB field .Status.CNT. Control_LoadPreset (BOOL, edge-triggered) is mapped to the Ctrl_HSC input of the CTRL_HSC instruction.

Verification Procedure

1. With the CPU in STOP, physically rotate the encoder shaft 10 revolutions. Note the mechanical count on the encoder body (e.g., 1000 PPR).
2. Go online with TIA Portal. In Watch table, add the HSC IDB tag CurrentValue. Switch the CPU to RUN.
3. Rotate the shaft 10 more revolutions. The CurrentValue should advance by 10 x PPR x evaluation factor. For a 1000 PPR encoder in 4x quad mode, expect 40,000 counts per shaft revolution.
4. Toggle the direction input. The count must decrement (or increment, depending on the mode and direction pin assignment).
5. Force the gate input low. The count value must freeze and resume on the next rising edge of the gate.
6. Trigger the Z (index) event. The HSC must generate one event pulse, and the IDB field EventStatus.Z_Event must be true for one scan.
7. Run the Online & Diagnostics → HSC view. TIA Portal will display the live count, the current direction, the gate state, and the last event timestamp.

Troubleshooting Matrix

Cross-Platform HSC Modules for Comparison

The S7-1200 HSC is sufficient for most machine-builder applications. For higher channel density, hot-swap I/O, or integration into a different control platform, the following modules are documented alternatives.

For S7-1500 and ET 200SP applications, the TM Count 2x24V technology module adds two independent HSC channels with onboard DI, DQ, and homing support. The TM Count 2x24V is documented in the SIMATIC ET 200SP Technology Module manual on the Siemens Industry Online Support portal. The legacy part number 6ES7-138-4DB03-0AB0 references the SSI module family for ET 200S; verify the current catalog number against the latest Siemens product catalog before ordering.

Performance and Sizing Notes

When selecting the CPU, the engineer should account for the OB1 scan overhead of the HSC processing. The HSC hardware latches the count on every edge, but the OB1 program that reads CurrentValue runs at the cycle time set under PLC → Properties → Cycle. For an HSC running at 200 kHz, the OB1 cycle time should be ≤ 1 ms to avoid lost edge evaluations when the value is used for control decisions. If the value is only displayed on an HMI and not used for control, a 10 to 50 ms cycle is acceptable.

For quadrature decoding, the effective count rate is 4x the encoder pulse rate. A 50 kHz encoder on each phase produces 200 kHz edge events per phase, and the HSC will increment the count at 200 kHz. Plan headroom accordingly.

FAQ