Siemens S7-300 Profibus Data Acquisition for Pulse Current Tests

1. Application Overview: High-Current Pulse Test Stand

The application addressed by this reference is a high-current switchgear test stand in which the digital Profibus output of an ABB IFOCS fiber-optic current sensor must be captured in synchronization with a 30 kA, 40 ms current pulse. The mechanical topology of the test article is as follows.

• Bypass Switch (BPS) or "main contacts": a normally-closed contact in parallel with the Vacuum Circuit Breaker (VCB). A pneumatic drive forces the BPS open at the start of a test; the resulting arc across the BPS is what the test is designed to handle.
• Vacuum Circuit Breaker (VCB): in parallel with the BPS. When the BPS opens, current commutates into the VCB, which then begins opening its own contacts.
• Counterpulse system: a bank of high-energy capacitor modules that fires an opposite-polarity current pulse approximately 2 ms after the VCB contacts part. The opposing pulse forces the arc current to cross zero and extinguish inside the VCB, which is the desired switching behavior.

With busbars at 30 kA peak and a total transient of approximately 40 ms, the role of the S7-300 PLC is to act as a Profibus data logger for the IFOCS, not as the test controller (that is hard-wired to protection relays and the capacitor-bank controller). The captured Profibus waveform is then compared offline with the waveform from a Rogowski coil reference on the same conductor to validate the IFOCS digital output.

The sampling requirement is 1.5–3 ms per sample, equivalent to 333–666 Hz. In a 40 ms window this yields 13–27 samples, sufficient to see the rise, peak, and decay of the pulse. The challenge is that the S7-300 must (a) read the IFOCS over Profibus, (b) do so deterministically at sub-3 ms intervals, and (c) buffer the result with full 32-bit consistency. The rest of this reference covers how to do that and what goes wrong if you do it wrong.

2. Profibus DP Protocol and Cycle Time Fundamentals

Profibus DP (IEC 61158 Type 3, IEC 61784-1 CPF 3) is a token-passing serial bus. Token-holding masters poll their assigned slaves in a deterministic cycle. The relevant timing parameters, all configured in STEP 7 HW Config under DP Master → Bus Parameters, are summarized below.

For a single-master, single-slave configuration with 16 bytes of cyclic I/O (typical of the IFOCS), the theoretical bus cycle is on the order of:

Tbus ≈ (overhead_bits + 11_bits/byte × 16_bytes) / baud_rate

At 12 Mbit/s this gives a frame payload of 176 bit-times, plus ~40 bit-times of SD/ED/FC/FCS framing and inter-frame gap, for ~220 bit-times total. The slave's turn-around is ~1–2 bit-times; the master's token handling is comparable. The theoretical single-slave poll is therefore ~250 bit-times, or about 21 µs at 12 Mbit/s. In practice, the S7-300 DP master uses a poll period of 1 ms minimum, so the effective bus cycle on the 300 series is governed by the master's poll period, not by the wire speed.

On a CP 342-5, the situation is different: the CP has its own Profibus stack and dual-port RAM, and the CPU exchanges data with the CP via FCs (DP_SEND, DP_RECV, or the older FC3/FC4 pair). The total round-trip from bus update to a value visible to the user program is in the 1–2 ms range because of the dual-port RAM handoff. This is the architectural reason for the "same value 8–16 times per OB1 cycle" symptom that appears in the field.

2.1 DP-V0 vs DP-V1 vs DP-V2 for acquisition

Profibus DP has three protocol versions. The relevant differences for a data-acquisition role are:

For a 1.5–3 ms sampling requirement, DP-V0 is sufficient and is the default. DP-V2 with isochronous mode is the right tool only if the requirement drops below 1 ms.

3. Siemens S7-300 CPU Selection for Fast Acquisition

The S7-300 family has roughly a 5:1 spread in scan performance. The most relevant CPUs for Profibus data acquisition are:

Three takeaways from this table.

1. Avoid the CP 342-5 for sub-5 ms logging. The CP is excellent for distributed I/O and slow cyclic data, but its dual-port RAM exchange adds 1–2 ms of latency between the bus and the user program. The integrated DP port on the 315-2 DP and 317-2 PN/DP exposes the process image directly to the CPU and removes that layer of latency.
2. The 313C is the bottleneck, not the bus. A 313C can be coerced into sub-10 ms logging with careful programming, but it is the slowest of the three and the only one that requires the CP 342-5. For a 30 kA pulse test, the 313C is the wrong CPU.
3. The 317-2 PN/DP is the preferred platform. It has the highest instruction throughput, an integrated DP master, and an integrated Ethernet port for post-capture buffer export via S7 put/get.

4. CP 342-5 vs Integrated DP Port: Architecture and Latency

The CP 342-5 is a Profibus DP master/slave module for the S7-300 backplane. It contains its own microprocessor, Profibus stack, and dual-port RAM. The CPU communicates with the CP via FCs such as DP_SEND and DP_RECV (or the older FC3/FC4 pair), which read and write the CP's dual-port RAM.

This architecture has three direct consequences for fast data logging.

1. Buffering between bus and CPU. The CP maintains the latest process image internally. Reading it from the CPU does not return a fresh value if the CPU reads more often than the bus updates the image. The diagnostic symptom is the one reported in the field: an application block (often called FC84 in user code) executes 8–16 times per OB1 cycle and returns the same value 8–16 times in a row. The repeated value is not a program bug; it is the bus update rate imposing a ceiling on the sample rate the user can actually see.
2. Data consistency. The CP's consistency mode (configured in HW Config) determines whether the CPU can read a partially updated multi-word value. For the 32-bit current value from the IFOCS, "Word consistency" or "Total length" must be selected; otherwise the read can return a value where the high word has been updated and the low word has not, producing a corrupted sample.
3. Exchange load. Every DP_SEND/DP_RECV call places load on the CP's internal task. If the application polls the CP faster than the bus updates the image, the CP is essentially answering the same question over and over, consuming CPU time on the CP side that could be spent on actual data exchange.

The diagnostic test is to maintain a "new-data" flag in the same buffer that advances only when the CP has a fresh bus frame. If the flag does not advance between consecutive DP_RECV calls, the symptom is confirmed as a CPU-faster-than-bus issue, not a program bug.

On the integrated DP port of the 315-2 DP and 317-2 PN/DP, the process image is updated directly in the CPU's memory by the integrated Profibus controller. Reads via PIW/PID are always word-consistent for the configured input length, and the user program sees a fresh value every time the DP controller updates the image, which on these CPUs is every 1 ms in the default configuration.

5. OB1 vs OB35: Choosing the Right Execution Context

The S7-300 has two relevant execution contexts for cyclic data acquisition.

For data acquisition, OB35 is the correct choice. The user program inside OB35 should do the bare minimum: read the process input, scale it, write to the circular buffer, increment the index. Anything else belongs in OB1.

Setting OB35 to 1 ms on a 317-2 PN/DP, with the OB35 code kept under 0.3 ms, has been demonstrated to reproduce a Rogowski coil reference waveform faithfully. On the 313C via CP 342-5, the same configuration does not produce a clean trace because the bus and CP layers are slower than the OB35 trigger.

5.1 Setting the OB35 phase offset

The OB35 phase offset (set in HW Config under CPU Properties → Cyclic Interrupts) lets you delay the first OB35 execution by a sub-period amount. A small offset (e.g., 0.2 ms) places the OB35 execution on a quiet part of the OB1 cycle, avoiding the process-image update phase. Recommended offset: 0.1–0.5 ms for a 1 ms OB35 period.

5.2 Detecting OB35 time error

If the OB35 code takes longer than the OB35 period, the CPU raises a diagnostic event and (depending on the OB35 error reaction setting) may stop the CPU. The diagnostic event has the identifier OB 35 time error and is visible in PLC → Diagnostics → Diagnostic Buffer. The fix is to either reduce the OB35 code, move non-critical work to OB1, or increase the OB35 period.

6. ABB IFOCS Profibus DP Integration

The ABB IFOCS is a fiber-optic current sensor. The optical head is mounted on the primary conductor; the electronics unit digitizes the optical signal, scales it, and publishes the result as a Profibus DP slave. The relevant interface characteristics are summarized below; the exact values are defined in the IFOCS installation manual and GSD file shipped with the sensor.

The GSD file (typical name ABB0FOCS.gsd) is provided by ABB and must be installed in STEP 7 (Tools → Install GSD File). The IFOCS then appears in the HW catalog under Profibus DP → Sensors → ABB. The slot configuration in the GSD must match the sensor's published assignment; if it does not, the slave enters "Parameter Fault" and the inputs read all zeros.

For a 30 kA primary, the IFOCS output is typically a 32-bit float in Amperes. The scaling is direct: a raw value of 30000.0 corresponds to 30 000 A. No additional user-side scaling is needed beyond a sanity-check range clamp (e.g., reject samples outside ±50 000 A).

7. Step-by-Step Configuration Procedure

7.1 Prerequisites

• STEP 7 V5.5 SP4 (or TIA Portal V13+ for a unified PC view)
• S7-300 CPU with integrated DP port (recommended: CPU 317-2 PN/DP, 6ES7 317-2EK14-0AB0 family, or CPU 315-2 DP, 6ES7 315-2AH14-0AB0 family)
• ABB IFOCS sensor with the Profibus DP option
• ABB IFOCS GSD file
• Profibus cable (Type A, twisted pair, shielded) and Profibus connector with built-in termination
• STEP 7 programming license for the S7-300

7.2 Install the GSD

1. Copy the GSD file (e.g., ABB0FOCS.gsd) into a local folder on the engineering station.
2. Open STEP 7 HW Config.
3. Tools → Install GSD File → browse to the file → OK.
4. Verify the IFOCS appears in the catalog under Profibus DP → ABB → IFOCS.

7.3 Configure the DP master

1. Insert a SIMATIC 300 station; add a rack and the chosen CPU.
2. Double-click the DP port → Properties → Operating Mode → DP Master.
3. Set the baud rate to 12 Mbit/s; set Ttr to 3000 bit-times.
4. Drag the IFOCS from the catalog into the master system.
5. Assign a unique Profibus address (default for IFOCS is 3; verify with the address switch on the sensor).
6. Open the IFOCS slot configuration and set the consistency to "Word consistency" or "Total length" for the 32-bit current value.

7.4 Configure OB35

1. CPU Properties → Cyclic Interrupts.
2. Set OB35 Execution to 1 ms.
3. Set the Phase Offset to 0.2 ms to avoid collision with the OB1 process-image update.
4. Set the OB35 error reaction to "OB only" (do not stop the CPU) for robustness.

7.5 Program OB35

The OB35 body should be a tight read-scale-store sequence. A typical skeleton in STL:

OB35 "Cyclic Interrupt"
    L     PIW  288          // First input word from IFOCS
    T     LW    0
    L     PIW  290          // Second input word
    T     LW    2
    L     LD    0           // 32-bit float, value in A
    ABS
    T     "DB_Capture".Sample[Idx]
    L     "DB_Capture".Idx
    +     1
    L     2000             // Buffer size = 2 s @ 1 kHz
    MOD
    T     "DB_Capture".Idx
    BE

The corresponding DB must be configured with the sample array as a REAL array of length 2000 (8 KB), and the Idx variable as a DINT.

7.6 Compile, download, and verify

1. Save and compile HW Config and the S7 program.
2. Download to the CPU.
3. Go online and check PLC → Diagnostics → Diagnostic Buffer for any OB35 time error or DP diagnostic events.
4. Use a test current source (or the Rogowski coil with a known AC waveform) to confirm the buffer captures a sensible trace.
5. Export the buffer to a PC via Industrial Ethernet (S7 put/get) or memory card.

8. Sample Rate Calculation and Bottleneck Identification

The effective sample rate of a Profibus-based acquisition loop is governed by three independent bottlenecks, and the slowest one wins:

fs = 1 / max( Tbus, Tob, Tprog )

Where:

• Tbus = Profibus cycle time (depends on baud rate, slave count, frame length, master poll period)
• Tob = OB35 configured period (1 ms minimum on S7-300)
• Tprog = OB35 execution time (must be less than Tob; otherwise the CPU reports OB35 Time Error)

8.1 Worked example: 1 kHz sampling on a 317-2 PN/DP

For a 40 ms pulse, this yields 40 samples — adequate for waveform reconstruction. If a higher sample rate is needed, the options are (a) move to a CPU with a faster OB35 minimum (the S7-300 series has no faster option), (b) move to Profibus DP-V2 with isochronous mode and the equidistant bus cycle, or (c) abandon PLC-based acquisition and use a dedicated Profibus data recorder such as a QuantumX DAQ node or a Delphin ProfiMessage that can sample at the bus-native rate.

8.2 Sample budget for a 40 ms pulse

9. Buffer Design, Data Consistency, and Post-Capture Export

9.1 Circular buffer pattern

For a 32-bit floating-point current value, the read in OB35 must be word-consistent. The integrated DP port on the 315-2 DP and 317-2 PN/DP supports word consistency for the configured input length automatically; the CP 342-5 requires explicit configuration in the slave's properties.

The recommended buffer pattern is a circular buffer of N samples with a write index that wraps modulo N. The standard S7-300 idiom is:

Idx_next = (Idx_current + 1) MOD N

with N = 2000 for 2 seconds of capture at 1 kHz. The DB is sized at N × 4 bytes = 8 KB, which fits comfortably in the S7-300 work memory (128 KB typical for the 317-2 PN/DP).

9.2 Buffer overflow handling

If the consumer of the buffer (e.g., a PC reading via S7 put/get) is slower than the producer (OB35), the producer will eventually overwrite unread samples. The mitigation is to add a "generation counter" that increments every time the buffer wraps; the consumer checks the generation counter between reads and rejects data acquired across a wrap boundary.

9.3 Post-capture export paths

10. Verification and Commissioning Procedure

10.1 Static verification

1. With the bus online, the IFOCS should report "Data Exchange" state in the DP diagnostic buffer (PLC → Diagnostics → DP Slave Diagnostics).
2. Inject a known DC current (e.g., 1000 A) through the IFOCS and read PIW; confirm the scaled value is within the sensor's accuracy class.
3. Verify zero offset: with zero primary current, the IFOCS output should be 0.0 ± accuracy class.

10.2 Dynamic verification

1. Mount a Rogowski coil on the same conductor as the IFOCS primary.
2. Condition the Rogowski signal with an integrator and feed it to a high-bandwidth oscilloscope (or a QuantumX DAQ node).
3. Trigger a 30 kA pulse and capture the S7 buffer to a file via Ethernet.
4. Compare the two waveforms; the Profibus trace should match the reference within the inherent 1 ms quantization error and the sensor's accuracy class.

10.3 Long-run stability

1. Run the OB35 capture for 1 hour at 1 kHz without a pulse trigger.
2. Inspect the buffer for stuck values, gaps, or out-of-range samples.
3. Check the diagnostic buffer for OB35 time errors, DP diagnostics, or communication errors.

10.4 Acceptance criteria

11. Troubleshooting Matrix and Field-Proven Caveats

11.1 Field-proven caveats

• Phase offset interaction with process-image update. On some firmware versions, the OB35 phase offset that places OB35 immediately after the OB1 PI update gives a stable sample; placing OB35 inside the PI update window can cause the read to return a partially updated value even with word consistency. Always test the offset empirically with a known pulsed current.
• CP 342-5 + OB35 is not enough. The CP 342-5 can update its dual-port RAM faster than OB35, but the bus-to-CP latency is still in the 1–2 ms range. Combining the CP 342-5 with OB35 at 1 ms gives a 1 kHz read rate but not a 1 kHz new-sample rate. For a true 1 kHz new-sample rate, the integrated DP port is required.
• Firmware version matters for OPC UA and memory card write-at-runtime. The S7-300 firmware is on a per-CPU basis; consult the Siemens product support pages for the exact firmware version that ships with the IFOCS Profibus option.
• Calibration and certification. The IFOCS may not be certified in all jurisdictions; if the test stand is used for regulatory certification of the breaker, a calibrated Rogowski coil should remain the primary reference and the IFOCS Profibus output should be treated as a secondary signal.

12. Frequently Asked Questions