Siemens S7-300: Comparing DWORD to Zero in STEP 7 (STL/LAD/FBD)

1. Problem Overview

Engineers integrating counters, piece counters, or scaled values from fieldbus partners frequently need to detect whether a 32-bit unsigned value (DWORD) on a SIMATIC S7-300 CPU has transitioned away from zero. The classic use case is a real-time parts counter: as long as the counter is greater than zero, an output, marker, or HMI tag must remain TRUE, and the program must capture the rising edge so that a downstream one-shot logic (e.g., a batch increment) fires exactly once.

Although STEP 7 STL, LAD and FBD all support DWORD natively, the comparison to a constant zero (L#0) is a 32-bit signed operation by default. This creates confusion for programmers who assume that a direct "MOVE" of a DWORD into a DINT will preserve the unsigned bit pattern. The MOVE box in LAD/FBD performs a type-checked copy, and on a CPU that does not accept the implicit conversion, the operation fails to compile or - worse - is silently coerced to zero in online monitor. The robust, language-agnostic solution uses three built-in STEP 7 statements: CLR, L, and >D (or <>D), followed optionally by FP/FN edge detection.

This article walks through the data-type theory, presents ready-to-paste STL, LAD/FBD and SCL code blocks, and finishes with a verification procedure and a troubleshooting matrix for the most common failure modes - including the MB200-MB255 scratchpad flag range and the LAD/FBD type-check switch.

2. Data Type Fundamentals: DWORD vs. DINT

STEP 7 defines several 32-bit data types that share the same 32 bits of memory but differ in how the CPU interprets those bits during arithmetic and comparison. The three that matter for this application are:

The CPU has no internal concept of "hex" - every operand is a 32-bit bit string. The interpretation as DWORD, DINT or REAL is selected entirely by the instruction that touches the accumulator. This is why a single MOVE of a DWORD into a DINT symbol does not convert; it just re-labels the same bit string, and any subsequent signed comparison can produce wrong results if the most significant bit (bit 31) is set.

For a piece counter that is always non-negative, the simplest and safest interpretation is unsigned 32-bit. Detecting "greater than zero" therefore reduces to detecting "not equal to zero" - because for an unsigned value, any non-zero bit pattern is necessarily > 0.

2.1 Bit-Level View of a Counter

Consider a parts counter holding the value 1 000 (decimal):

• Hex: W#16#0000_03E8 or DW#16#000003E8
• Signed 32-bit (DINT) view: +1000
• Unsigned 32-bit (DWORD) view: +1000

Now consider a counter holding 4 300 000 000 (decimal):

• Hex: DW#16#0000_0001_0042_C1A0
• Signed 32-bit (DINT) view: +4300000000 - this is out of range for DINT (max 2 147 483 647) and would be flagged as a compiler error or wrap to a negative value.
• Unsigned 32-bit (DWORD) view: +4300000000 - valid.

For a counter that will never exceed 2 147 483 647 parts, the DINT-signed comparison >D against L#0 works flawlessly. For counters that can exceed 2.1 billion, the correct unsigned comparison is the 32-bit bit-pattern test <>D against L#0 or, more strictly, a direct test of the most significant bit and the byte 0 ORed across all four bytes.

3. Prerequisites

Before editing the project, confirm the following:

1. STEP 7 V5.5 or V5.6 (classic) is installed with the S7-300 optional package. TIA Portal can also be used, but the symbol naming and offline/online behaviour differ; this article uses classic STEP 7 conventions.
2. The CPU firmware supports the symbol's declared data type. A CPU 312C, 313C, 314, 315-2 DP, 317-2 or 319-3 is sufficient. Reference: SIMATIC S7-300 CPU 31xC and CPU 31x Operating Instructions (Siemens KB 91696622).
3. The counter source - a DB field such as DB100.DBD114, an I/Q area, or a value received from a PN/DP partner - is already declared with the correct data type (DWORD or equivalent 32-bit area).
4. The destination marker (M bit) and any auxiliary M bits (FP/FN helpers) are not inside the reserved range MB200-MB255 used by some S7-300 CPUs as scratchpad flags. Use M0.0-M199.7 or M256.0-M4095.7.
5. PG/PC is online (MPI, PROFIBUS or PROFINET) so the result of the comparison can be monitored with Monitor/Modify (VAT) or with the program status.

4. STL Implementation: The Three-Instruction Solution

Statement List (STL) gives the most direct access to the two accumulators (ACCU 1 and ACCU 2). The reference pattern is the canonical "compare-DWORD-to-zero-and-set-marker" snippet:

// Compare DWORD "RealizedQuantity" against L#0 and set M199.0 when > 0
CLR                              // ACCU 1 = 0, RLO = 0
L   "RealizedQuantity"           // ACCU 1 := DWORD, ACCU 2 := 0
L   L#0                          // ACCU 1 := 0, ACCU 2 := DWORD
>D                               // RLO = 1 if ACCU 2 > ACCU 1 (signed 32-bit)
=   M 199.0                      // Marker follows RLO

Instruction-by-instruction trace:

1. CLR sets the RLO (result of logic operation) to 0 and clears ACCU 1. This is required only when the preceding network leaves a residual value in ACCU 1 that could interfere; modern programmers include it for hygiene.
2. L "RealizedQuantity" loads the 32-bit bit string of the source symbol into ACCU 1. The old ACCU 1 shifts to ACCU 2. The data type tag of the symbol tells STEP 7 to load it as a 32-bit value, but the bits are not reinterpreted.
3. L L#0 loads the constant L#0 (DINT zero) into ACCU 1; ACCU 2 keeps the counter value.
4. >D performs a 32-bit signed compare: if ACCU 2 > ACCU 1 the RLO becomes 1, otherwise 0.
5. = M 199.0 assigns RLO to the marker coil.

For the more robust unsigned case use <>D (not equal):

CLR
L   "RealizedQuantity"
L   L#0
<>D
=   M 199.0

<>D is true for any non-zero bit pattern, including the value 4 294 967 295 (all 32 bits set) which would otherwise look like -1 in signed interpretation. For piece counters this is the recommended form.

4.1 Full STL Block With Edge Detection

// Network 1: Continuous "> 0" flag
CLR
L   "RealizedQuantity"          // DB100.DBD114, DWORD
L   L#0
<>D
=   M 199.0                     // M 199.0 = 1 when counter <> 0

// Network 2: Rising-edge one-shot (FP)
A   M 199.0
FP  M 199.1                     // M 199.1 = previous state of M 199.0
S   M 199.3                     // Set M 199.3 on rising edge

// Network 3: Falling-edge one-shot (FN)
A   M 199.0
FN  M 199.2                     // M 199.2 = previous state of M 199.0
R   M 199.3                     // Reset M 199.3 on falling edge

The FP (Flank Positive / rising edge) and FN (Flank Negative / falling edge) instructions need their own helper bits because the previous-cycle state must be remembered. M 199.1 and M 199.2 are edge memory bits and must be assigned exclusively to one FP/FN pair. The reference description of FP/FN is in the STEP 7 Programming and Operating Manual, section on bit-logic instructions.

5. LAD/FBD Implementation Using the Comparator Block

In LADDER (LAD) and FUNCTION BLOCK DIAGRAM (FBD), the comparator CMP >D or CMP <>D block is dragged from the comparator folder of the program-element catalog. Wire the inputs as follows:

Steps to insert the comparator:

1. Open the target block (OB1, OB35 or FC) in LAD or FBD.
2. From the program-element tree, expand Comparator and select CMP <>D.
3. Drop it on an empty network. STEP 7 will auto-create the input and output placeholders.
4. Click the IN1 placeholder, type the symbol name (e.g., "RealizedQuantity").
5. Click the IN2 placeholder, type L#0.
6. Click the output and type M 199.0 or any BOOL marker.
7. Save the block and download to the CPU.

For edge detection, insert FP from the bit-logic folder after the comparator output, and wire a S (set) coil to a retention marker such as M 199.3. The companion FN/R pair resets the same marker when the comparator returns to zero.

6. SCL Implementation for Compact Code

Structured Control Language (SCL) lets you express the same logic in two lines. Open a new source file or FC, change the language to SCL, and type:

// SCL: edge-detected comparison
IF "RealizedQuantity" <> DWORD#16#0 THEN
    "CounterActive" := TRUE;
ELSE
    "CounterActive" := FALSE;
END_IF;

IF "CounterActive" AND NOT "CounterActiveOld" THEN
    "NewBatchEvent" := TRUE;          // rising-edge event
END_IF;
"CounterActiveOld" := "CounterActive"; // edge memory

Notes on the SCL syntax:

• Use the DWORD#16#0 literal for an unsigned 32-bit zero. The L#0 literal from STL is also accepted in SCL as a DINT zero, but DWORD#16#0 documents the unsigned intent more clearly.
• SCL automatically generates the FP/FN edge memory block; you do not need explicit auxiliary flags.
• The SCL compiler produces STL internally, so the resulting MC7 code is identical in size to the hand-written STL of Section 4.

7. Edge Detection: FP and FN Instructions

Continuous comparison is rarely the final logic. Typical consumer blocks only want a one-shot pulse on the rising edge of the comparator (e.g., increment a batch counter, log a tag change, fire a one-shot output). The combination of FP and FN provides exactly that.

Both instructions require an edge memory bit whose address must be unique to that instruction. Reusing the same edge-memory bit for two FP blocks causes one of the edges to be lost. A common convention is to reserve M 100.0-M 199.7 as a scratch area for FP/FN helpers, leaving M 0.0-M 99.7 free for global flags and M 200+ free (avoiding the scratchpad range, see Section 8).

8. Scratchpad Flag Warning: Avoid MB200-MB255

Several S7-300 CPUs reserve MB200-MB255 as internal scratchpad memory for the operating system. On the S7-31xC series, the system uses bits in this range for communication diagnostics, time-stamping and internal scheduling. The exact behaviour depends on firmware version:

If the application places the FP helper or the continuous-flag marker inside this range, the OS can overwrite it on every OB1 cycle. The result is unpredictable: the marker may flicker, FP may never fire, or FN may fire repeatedly. The fix is to relocate the bits:

• Use M 0.0 to M 199.7 for the user program.
• Or use M 256.0 to M 4095.7 (large S7-300 CPUs allow 4 KB of M area; verify the technical data of your CPU).
• For retentive flags, configure the M-retentive area in HW Config > CPU Properties > Retentive Memory and avoid the scratchpad area.

9. Type Check Toggle in STEP 7 LAD/FBD

STEP 7 enforces type checking in LAD and FBD by default. If the comparator pin expects DINT but the symbol is declared as DWORD, the editor will refuse the wire. There are two legitimate ways to resolve this:

1. Preferred - change the symbol's data type to DINT if the value can never exceed 2 147 483 647. This is the cleanest fix and removes the type mismatch permanently.
2. Temporary - disable type checking for this network. Open Options > Customize > LAD/FBD and uncheck Type Check of Address. The compiler will accept the wire, but the program becomes prone to silent errors: a REAL wired into a DINT pin will be misinterpreted as a 32-bit bit string instead of triggering a clear compile error.

10. Online Monitoring and Debugging

To verify the logic is live on the CPU, use the standard STEP 7 monitoring features:

1. Program Status (LAD/FBD/STL) - right-click inside the block and select Monitor. The comparator highlights green when its result is 1, the marker M 199.0 is shown in dark blue (TRUE) or grey (FALSE).
2. Monitor/Modify (VAT) - create a Variable Table (VAT) with three rows: the source DWORD, M 199.0, and M 199.3. Click the Monitor button. Force the source to DW#16#0 with Modify, then to DW#16#1 - the marker should toggle 0→1 and the M 199.3 one-shot should fire exactly once.
3. Reference Data - Options > Reference Data > Display shows every location where M 199.0 is read or written, helping to track down overwrites.
4. Cross-reference for FP/FN - confirm that the edge-memory bits M 199.1 and M 199.2 are not referenced anywhere else in the program.

10.1 Forced Value Test Pattern

Use the following sequence in Monitor/Modify to validate every path:

11. Verification Procedure

Once the logic is on the CPU, perform the following commissioning checks before handing the system to production:

1. Confirm the counter is being updated as expected by reading RealizedQuantity in the VAT. The hex view should change with every counted part.
2. Toggle the comparator to 1 by setting the source to 1, then back to 0. The M 199.0 flag must follow in real time.
3. Watch M 199.3 (the one-shot) for at least 10 seconds with the counter held at 0. It must stay 0. Then increment the counter by 1 - M 199.3 must pulse high for one OB1 cycle.
4. Power-cycle the CPU (STOP→RUN via mode switch or power OFF/ON). Verify that the M-bit state is consistent with the configured retentive behaviour. By default, M flags are non-retentive, so M 199.0 will be 0 after a cold restart regardless of the source value.
5. Trigger a diagnostic OB (OB82, OB85, OB121) and confirm that no M bit in the 200-255 range is touched by the OS.

12. Troubleshooting Matrix