Siemens S7 PLC Instruction Execution Time Reference Tables

Overview of Instruction Execution Time in PLC Systems

Instruction execution time is the duration a programmable logic controller CPU requires to fetch, decode, and complete a single user-program instruction, expressed in microseconds (µs) or nanoseconds (ns). It is the fundamental atomic component of total scan time, the metric that drives cycle-period specification, interrupt latency, and deterministic I/O response. For engineering decisions, the published execution time of each instruction class — bit, word, fixed-point, floating-point, compare, conversion, shift, timer, counter — establishes an upper bound on what a given CPU can sustain at a target cycle period.

Manufacturers publish these values under controlled benchmark conditions. The reported number represents typical execution for a fully-compiled instruction at a defined firmware revision, normally with immediate (direct) addressing and no error conditions. Real values vary with operand type (byte/word/dword, real, lreal), addressing mode (direct, indirect, DB, M, I, Q, L), data length, CPU workload, communication load, and bus topology. The published number is therefore best treated as a specification floor and a basis for comparison, not a guaranteed worst-case.

Three common reference units appear in vendor documentation:

• Absolute time (µs, ns) — Siemens S7-1200 and S7-1500 system manuals, Allen-Bradley Logix RM002.
• Clock cycles — historic Siemens S7-300/S7-400 instruction list, often listed alongside µs.
• Bits per second / words per second — derived marketing metrics not used in this reference.

How Siemens Publishes Execution Time Data

Siemens distributes instruction execution time in three document classes, all reachable from the Siemens Industry Online Support portal at support.industry.siemens.com:

1. Instruction List manuals — one per CPU family. Each row contains the instruction mnemonic (German LAD/FBD/ST), a short description, the operand types supported, and the typical execution time in µs or ns for the affected CPUs.
2. CPU Specifications / System Manual — includes an "Instruction execution times" table that aggregates the most-used operations (bit, word, fixed-point, floating-point) for the entire CPU line covered by the manual.
3. CPU Datasheet — short-form values, usually 6–12 rows, for the most common operations. Used for quick vendor comparisons.

When a firmware revision changes CPU behavior, the instruction list and datasheet are re-issued. Always cite the firmware version alongside the time value. The legacy ST-70 catalog (SIMATIC S7 reference catalog) historically bundled the execution-time tables for the whole S7 family; it has been superseded by the per-family manuals in current support.

S7-300 Instruction List Reference

The S7-300 instruction list covers the discrete and compact CPUs, plus the ET 200S IM 151-7 / IM 151-8 / IM 154-8 interface modules that act as masters in distributed I/O. The manuals are:

• S7-300 Instruction List (CPU 312, CPU 314, CPU 315-2 DP, CPU 315-2 PN/DP, CPU 317-2 PN/DP) — covers the standard 31x range.
• S7-300 Instruction List (CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU) — covers the F-CPUs, fail-safe, and the BM/IM CPU variants.
• S7-300 CPU Specifications (CPUs 312 IFM to 318-2 DP) — legacy aggregate document with execution times for the 312 IFM through 318-2 DP line.

Search the Siemens support portal with the document type "Instruction List" filtered to product "SIMATIC S7-300" for the most current entry ID. Representative content layout for the S7-300 instruction list:

The exact figures must be read from the manual. The relative ratios between CPU classes remain consistent: a CPU 317-2 PN/DP is typically three to four times faster than a CPU 314 on bit operations and two to three times faster on floating-point operations. Compact C-CPUs (314C-2 PN/DP, 315-2 PN/DP, 317-2 PN/DP) carry the same execution times as their discrete counterparts of the same generation; the C designation adds integrated I/O and technological functions without altering the CPU arithmetic core.

S7-400 Instruction List Reference

The S7-400 instruction list covers the high-end CPU 412, 414, 416, 417 families. These CPUs are designed for large program volumes and tight cycle periods; their arithmetic unit is wider and the instruction fetch path is decoupled from the working memory access.

• S7-400 Instruction List (CPU 412, 414, 416, 417) — discrete and H variants, with two manual revisions covering both the original and PN-CPU generations.

Typical execution times for the S7-400 family, drawn from the CPU specifications section of the system manual:

Multi-CPU configurations in the S7-400 (rack with CPU 417 + CPU 417, or 416 + 414 combinations) allow program partition. Execution times per instruction do not change, but total throughput scales roughly linearly with the number of active CPUs. Synchronization points (OB 60 / OB 61–64) introduce wait cycles; the published execution times do not include synchronization wait.

S7-400H Redundant System Execution Times

The H-system instruction list covers the fail-tolerant / redundant CPUs CPU 412-3H, 414-4H, 417-4H. Values for the 410H are published in a separate datasheet. The redundant firmware adds cross-link synchronization events that increase the effective execution time of OB 1, OB 35, and any OB that updates I/O shared between the two halves of the H-system.

The Siemens publication "SIMATIC S7-400H Fault-Tolerant Systems" lists both the base execution time and the effective time under redundancy, the latter typically 5–10% higher for OB 1 cycle operations and up to 25% higher for tight cyclic interrupt OBs depending on the configured maximum runtime. Application programmers must use the redundant-mode figures when sizing cycle periods for H-systems; using the non-redundant S7-400 figures leads to systematic scan-time overshoot that can only be caught at commissioning.

S7-1200 Instruction Execution Times

The SIMATIC S7-1200 Programmable Controller System Manual, available from the Siemens support portal (entry ID 109741593 at the time of writing, see SIMATIC S7-1200 System Manual), contains the complete instruction execution time table for the entire S7-1200 line, CPUs 1211C through 1217C. The table is indexed by instruction class and lists one value per CPU model.

Representative excerpt (verify against the current revision of the manual):

Within a single S7-1200 firmware generation, the execution time per instruction class is constant across CPU models — the larger CPUs add work memory, I/O bandwidth, and communication channels, but not ALU performance. The upgrade path from CPU 1211C to 1217C is therefore a memory/capability upgrade, not a speed upgrade.

S7-1500 Instruction Execution Times

The SIMATIC S7-1500 Automation System System Manual, available at SIMATIC S7-1500 System Manual, publishes the most detailed per-instruction table in the Siemens lineup. The S7-1500 uses a consistent backplane, but the CPU arithmetic performance scales with the CPU class:

For motion and complex math, the S7-1500 also publishes a "Technology objects" performance figure (for example, TO_SpeedAxis / TO_PositioningAxis in the manual). These are not instruction execution times in the classical sense but cycle-budgeting values for a single axis update at a given CPU class.

The compact CPUs CPU 1511C, 1512C share the bit/word performance of the 1511-1 PN but include integrated analog and digital I/O. The CPU 1510SP-1 PN (ET 200SP CPU) has slightly slower execution times than the 1511-1 PN due to its restricted thermal envelope; the system manual lists the actual deltas.

Cross-Platform Comparison: Siemens vs Allen-Bradley

Engineers frequently compare S7 execution times against Allen-Bradley / Rockwell Logix 5000 controllers. The Allen-Bradley reference document is "Logix 5000 Controllers Instruction Execution Times", publication logix-rm002, available at Logix RM002. It provides estimated execution times for instructions when executed in a Studio 5000 Logix Designer project on a given controller family (CompactLogix 5380, ControlLogix 5580, etc.).

For consistent comparison, restrict the comparison set to one instruction class (for example "Add, DINT") and one operand type (DINT vs REAL) at the same CPU generation tier. Selected published data points from the Logix RM002 reference (verify against the current revision):

For meaningful vendor comparison:

1. Match generation (S7-1500 vs ControlLogix 5580, not S7-1500 vs SLC 500).
2. Match operand width (DINT vs INT, REAL vs LREAL).
3. Match address mode (Logix tag-direct addressing is closest to S7-1500 symbolic I/O or DB access).
4. Account for scan overhead. Logix RM002 gives per-instruction times; total scan includes task scheduling, communication servicing, and motion planner — all of which differ between platforms.

As a general rule, current-generation S7-1500 CPUs (CPU 1518-4 PN/DP) deliver bit-instruction performance in the single-digit nanosecond range, which is at or below the best published Logix 5580 per-instruction value. Floating-point-heavy workloads favor the S7-1500 at the high end (CPU 1518 / CPU 1519) because of the wider internal datapath and integrated trigonometric acceleration in the CPU 1518-4 PN/DP MFP variants.

Influencing Factors on Real-World Execution Time

Published values are baseline numbers. Real scan-time contribution from each instruction depends on several factors the engineer must control for in the sizing spreadsheet:

The scan time displayed in TIA Portal (online > diagnostics > scan cycle time) reflects the integrated effect of all of the above and is the only fully reliable number for a given project.

Engineering Decision Framework for CPU Selection

Selecting a Siemens CPU on the basis of instruction execution time is a four-step procedure:

1. Quantify the workload. Estimate the number of bit, word, fixed-point, and floating-point instructions per scan using the program structure (number of FB instances, call depth, IF/CASE/SWITCH density). Avoid scaling from a non-representative microbenchmark.
2. Apply the published times. Multiply each instruction count by the published execution time for the candidate CPU. Sum to obtain the theoretical scan time.
3. Add overheads. Add 20–30% margin for Profinet servicing, web server, OPC UA, and online services. Add absolute time for the OB 1 process image update (typically 50–200 µs for the first 1024 I/O).
4. Verify against the cycle time setpoint. If the calculated scan exceeds 50% of the cycle time setpoint, move to the next CPU class. If it exceeds 80%, two CPU classes. If the application is motion-critical, target 25% of the cycle time setpoint.

For applications that demand very short cycle periods (< 1 ms), an S7-1500 CPU 1516 or higher is required; S7-1200 and S7-300 CPUs cannot sustain such cycle periods regardless of program size.

Verification and Benchmarking Procedures

After CPU selection, confirm the choice by measurement on the target hardware:

1. Set up the project at full size. Compile a representative program (do not benchmark with the ladder stub).
2. Use the S7-1500 / S7-1200 trace to record OB 1 cycle time over 1000 cycles. Capture minimum, maximum, and average.
3. Apply the production communication configuration. Run the same Profinet topology and Profinet update time as the final machine. The published instruction times do not include the Profinet update window.
4. Stress test. Force all analog inputs to a sweeping value to defeat compiler-side constant folding. Verify the maximum scan time is still within budget.
5. Add diagnostic blocks. Use the "RD_SINFO" / "RDSYSST" instructions to read scan time statistics in OB 1 and report them on the HMI. This is a permanent runtime monitor.

The standard ST-70 catalog (where still available) provides a single-page quick reference, but the per-CPU system manuals are the authoritative source and should always be cited in design documentation.

Common Pitfalls and How to Avoid Them

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