Siemens STL L T A Instructions: Peripheral I/O in TIA Portal

Overview

SIMATIC STL (Statement List) is the IEC 61131-3 textual programming language still shipped with every S7-300, S7-400, and S7-1500 CPU. Although TIA Portal promotes ladder logic (LAD), function block diagram (FBD), and structured control language (SCL) as the first-class citizens, STL remains the lingua franca for migrating legacy STEP 7 V5 projects, debugging low-level scan-order issues, and writing tight bit-manipulation routines where ladder contacts would obscure intent. Two questions dominate every introductory STL thread on the Siemens Industry Online Support portal:

1. What do the single letters L, T, and A actually do in a snippet of STL code?
2. Why does Siemens expose two address types for the same physical input — for example IB 4 versus PIB 4?

This reference answers both at a level appropriate for a commissioning engineer who can read ladder logic but has not written STL before. It documents the meaning of L, T, and A, the difference between the process input image (PII) and the peripheral area, the canonical addressing syntax in TIA Portal V14 and later, and the boundary cases that make peripheral access a sharp tool rather than a default approach. Field-proven caveats — including why writing to inputs (T IB) is a recognised but discouraged pattern — are spelled out in the closing section.

The reference pattern that motivates this article is taken from the official Siemens support article "Where and when do you need peripheral addressing?", which uses the three-letter stub:

L   PIB  204
T   IB    4
A   ...

Each line corresponds to one of the STL fundamentals; subsequent sections decode the snippet, expand each instruction into its alternatives, and show how to verify it under TIA Portal’s online monitor.

Prerequisites

• TIA Portal V14 SP1 or later installed, including the optional "STEP 7 Professional" package that ships the STL editor (LAD/FBD/STL buttons on the toolbar).
• A project containing at least one S7-1500 CPU, S7-300 CPU, or S7-400 CPU. S7-1500 is preferred because STL under TIA Portal V14 is first-class; S7-300/400 STL imports from STEP 7 V5 project archives (.s7p or converted .ap14) and recompiles cleanly.
• Familiarity with boolean logic operations (AND, OR, NOT) and the idea of a binary contact (NO / NC) in ladder logic.
• Access to the Siemens Industry Online Support portal for cross-reference against the canonical FAQ 18325417 on peripheral addressing and FAQ 109736536 on shared-device / MSI / MSO configuration.

STL Mnemonic Meanings: L, T, A

In STL, every line is an instruction that operates on one of two 32-bit accumulators (ACCU 1 and ACCU 2) or on the binary result of logic operation (RLO) flag. The three letters from the source snippet decode as follows:

Three observations follow directly from the table:

1. L and T are scalar, addressing bytes, words, or double words indiscriminately. A is restricted to a single bit operand (or its negated form AN).
2. T never alters ACCU 1 or ACCU 2; it is purely a one-way memory write.
3. A does not load a value into ACCU 1 — it only updates the RLO. To read a bit value into ACCU 1 you must use L with a byte/word/double-word operand (for example L IB 4 places the byte at process-image address 4 into ACCU 1, and you can then manipulate the bit of interest with A, O, or X on a derived mask).

The canonical reference pattern from the source can therefore be parsed mechanically:

L   PIB 204       // Load Peripheral Input Byte at byte address 204 into ACCU 1
T   IB    4       // Transfer ACCU 1 to process-image Input Byte 4
A   M   10.0      // AND-test bit M 10.0 (RLO := RLO AND M 10.0)

The first line reads the current physical state of a remote I/O byte directly from the backplane or PROFINET slot, bypassing the OB1 process image. The second line deposits that byte into the local process image at IB 4, replacing whatever the cyclic OB1 update placed there. From that point forward, every A I 4.x, L IW 4, or comparison against IB 4 in the same cycle sees the freshly copied value rather than the cycle-stale image. The third line reads from bit memory — not from process I/O — to decide the next branch.

Why the mnemonic A instead of AND

Siemens STL was designed in the 1980s when every CPU instruction needed to fit into a tight instruction word. Dropping the trailing "ND" shrank the opcode and the parser surface without sacrificing semantic clarity. The German mnemonic convention uses U (from UND) and O (from ODER) for AND / OR. International projects switch mnemonics under “Options > Settings > International” in TIA Portal (and under “Tools > Options > Customise > Mnemonics” in STEP 7 V5). The semantic meaning of L, T, and A is identical in either locale.

Process Image vs. Peripheral I/O Access

Every S7 CPU maintains two views of the same physical inputs and outputs. The table below maps the address prefix used in STL onto the CPU’s view of the same byte.

The two views are illustrated below.

When peripheral access is the right choice

• The I/O area exceeds the configured process image size for that CPU (for example, a remote PROFINET station with addresses 0…32767 where only 0…1023 are mapped into the PII).
• The application must read fresh data from a fast-changing signal — such as a high-speed counter or a motion encoder — within the same OB1 cycle that produced the request, rather than waiting for the next cycle boundary.
• The application is time-deterministic relative to a hardware event and cannot tolerate the jitter caused by PII snapshotting.
• The application needs sample-and-publish behaviour: it captures a peripheral input as a snapshot, writes it back into its own process image area, and downstream logic operates on the stable value for the rest of the cycle.

When peripheral access is the wrong choice

• Multiple OBs read the same input — every direct read returns a different physical value, producing inconsistent states within the cycle.
• Outputs are written to from multiple interrupt OBs — direct peripheral writes do not merge cleanly with the PIQ buffer.
• The code is intended to be portable to other SIMATIC platforms; sticking to the process image keeps the addressing pure and reusable.
• The application can tolerate up to one OB1 cycle of latency on that signal.

STL Operand Areas and Data Widths

STL addresses operands with a letter (or letter pair) for the memory area, an optional data-width suffix (B byte, W word, D double word), and the integer address. A trailing dot followed by a bit number addresses a single bit. The supported areas are:

Address-byte alignment matters. STL never enforces it for you — the T IB 4 line from the source is valid even though semantically it overwrites a previously buffered input byte. If you substitute a word transfer, address increments by two (for example T IW 4 writes bytes 4 and 5). A double-word transfer increments by four. Where the hardware requires word alignment (for example, analog channels mapped to peripheral words above byte 0), the configurator in TIA Portal enforces the alignment automatically; in raw STL imports, verify that the chosen address does not split a multi-byte channel.

Mixed-size transfers

Loading a 16-bit PIW into the 32-bit ACCU 1 leaves the upper 16 bits zero-extended. Loading a 32-bit PID uses all 32 bits. Transferring a 32-bit MD to a 16-bit MW truncates — only the low 16 bits land in the destination. STL silently performs these truncations; nothing is flagged at compile time, so a wrong transfer width is a common source of “value looks wrong but compiles fine” bugs.

TIA Portal STL Configuration Walk-Through

This procedure produces the exact L / T / A pattern from the source on an S7-1500 CPU using TIA Portal V14.

Step 1 — Enable STL on a code block

1. In the project tree, right-click “Program blocks” and choose “Add new block > Function block” (or open an existing FB).
2. Open the block, then choose “View > STL” from the menu (or click the STL button on the toolbar).
3. If the menu item is greyed out, open the project properties and select “STEP 7 Professional” as the programming package; reinstall if necessary. TIA Portal “Basic” does not include STL.
4. Verify the block’s general properties show “LAD/FBD/STL” enabled for the chosen language combination (LAD/FBD, FBD/STL, or STL only).

Step 2 — Declare the working variables

Declare one input at the start of the FB so the L instruction has a typed operand. The block interface below uses symbolic names; TIA Portal resolves them to absolute addresses during compilation.

Step 3 — Add the STL source segment

Inside Network 1 of the FB, paste the following STL code. Comments after // explain each line.

// Network 1: refresh local mirror from peripheral input 204
L     PIB   204               // ACCU 1 := remote input byte at slot 204
T     MB    100               // MB 100 mirror for bit-level testing

// Network 2: bit test and branch decision
A     M   100.0               // RLO := RLO AND M 100.0  (first-check load)
JC    _BitSet                 // Jump if RLO = 1
JU    _BitClr                 // Otherwise jump to clear

_BitSet:
SET                            // Make RLO = 1 explicitly
S     #checkBit
JU    _End

_BitClr:
CLR                            // Make RLO = 0 explicitly
R     #checkBit
_End:  NOP   0

For an even tighter pattern that mirrors the source snippet exactly, drop the staging MB write and replace T MB 100 with T IB 4 — but only if you are inside a Siemens library that documents the pattern as intentional. Otherwise the safer choice is T MB 100 as shown above, because writing to a process-image input byte is a non-default operation that confuses the OB1 read-back path during the next cycle.

Step 4 — Compile, download, and go online

1. Click “Compile > Software (rebuild all)”. Resolve any syntax errors; TIA Portal flags spurious A operations on byte operands with a “Bit operand expected” message and flags A on non-boolean tag types with “Operand type not permitted”.
2. Click “Download to device > Software and hardware configuration”. Confirm that the CPU is in STOP for the initial download, or that TIA Portal negotiated a “RUN” hot reload for the target firmware. S7-1500 supports online block changes from RUN; S7-300/400 require a STOP download for most STL block changes.
3. Right-click the block and choose “Monitor / modify > Monitor (STL)”. The window now shows the current ACCU 1, ACCU 2, RLO, BR, OV, OS, CC 0, and CC 1 status bits line by line as each statement executes.
4. To force a value (for example, to simulate a stuck input), open “Force table” via “Watch & force tables” and insert a forced input. Verify the operand type matches; STL expects bit operands on A and integer operands on L.

Verification and Online Diagnostics

The STL monitor view in TIA Portal exposes the runtime state line by line. The colour map and meaning are:

For cyclic verification, drop a counter into a test block: every A M 100.0 that returns 1 must increment the counter by exactly one per OB1 cycle. If the increment is random, the input is changing mid-cycle — switch from peripheral access back to the process image to confirm whether the bug is real-time noise or programming jitter.

Troubleshooting matrix

Bit Testing with the A Instruction

The A mnemonic does far more than “load a bit”. It is the foundation of every STL boolean network. The full family of bit-test instructions is:

A complete STL network equivalent to a ladder rung with two NO contacts in series and an output coil looks like this:

A     I   0.0        // First contact - first check loads I 0.0 into RLO
A     I   0.1        // Second contact - RLO := RLO AND I 0.1
=     Q   8.0        // Drive output Q 8.0 if both inputs are "1"

A rung with two NO contacts in parallel:

O     I   0.0        // First parallel - first check loads I 0.0 into RLO
O     I   0.1        // Second parallel - RLO := RLO OR I 0.1
=     Q   8.0

A mixed series / parallel rung with a final NC contact:

A     I   0.0
A     (              // Open parenthesis for the OR chain
O     I   0.1
O     I   0.2
)                    // Close parenthesis restores the host AND chain
AN    M    5.3       // NC contact on flag M 5.3
=     Q   8.0

First-check / RLO edge

The first A, O, X instruction in a network does not AND/OR/XOR anything — it simply loads the state of the addressed bit into the RLO. From the second instruction onward, the operation is RLO := RLO <op> operand_bit. Treat the first line of every network as “first check” and every subsequent line as an accumulation. To override that initialisation, use:

• SET — set RLO = 1 unconditionally
• CLR — set RLO = 0 unconditionally
• NOT — invert the current RLO
• SAVE — copy the current RLO into the BR (binary result) bit for use by other blocks

Edge-detected bit tests (FP and FN)

Beyond the combinational A, STL exposes FP (rising-edge detect) and FN (falling-edge detect). Internally FP maintains a per-operand edge bit; the RLO is set to 1 only when the current operand state is “1” and the previous scan was “0”. This is the STL equivalent of a ladder P-contact.

A     I   0.0
FP    M   100.0       // M 100.0 must be a non-retain flag reserved for the edge bit
=     M   50.0        // Edge flag ready for further use

PROFINET and Multiple Shared I/O Context

The same L / T / A building blocks become meaningful in a multi-controller PROFINET topology when one of the controllers wants to read inputs owned by another controller. The IO Device publishes those inputs as “shared inputs” under the Multiple Shared Input (MSI) feature, and consuming controllers reach them via the same peripheral-or-process-image access pattern.

For the canonical “read inputs from a second S7-1500 controller across PROFINET” workflow, see Siemens FAQ 109736536 on shared-device and MSI / MSO configuration in TIA Portal. The configuration property “Copy from controller” lights up only when the IO Device has been set to operate in shared-device mode with at least two controllers assigned and an MSI slot range defined; if the option is greyed out, revisit the IO-Device assignment table first.

In STL, the consumer-side logic is unchanged:

L     PIB   204        // Shared input byte from the partner controller
T     MB    110        // Local mirror in bit memory
A     M   110.3        // Test a single bit of the shared input
=     Q   12.7         // Drive a local output

Solid arrows denote the controller that owns a particular slot; dashed arrows denote MSI-consumer links that read the same data without owning it. Each consuming controller downloads its projection of the shared device, then accesses the corresponding slot addresses locally — either via the process image or, for time-critical work, via L PIB as above.

Common Pitfalls and Field-Proven Caveats

• Writing to inputs is rarely meaningful. Inputs are sourced by the field wiring. A T IB x only makes sense when the destination IB is mirrored back through a documented library function — never blanket. Use T QB x if you intend to drive an output, or T MB x if you want scratch memory.
• Mixing bit and byte operators in one statement chain. Always use A (or O, X) for single bits and L / T for bytes, words, and double words. The compiler accepts L IB 4 followed by A M 4.0, but not A IB 4 — a byte operand is not a bit operand.
• Byte alignment of word and double-word transfers. L PIW 5 on an odd peripheral address overlaps bytes 5 and 6 on most backplane buses; either reserve even addresses or move the whole block to a clean offset.
• Cycle time of repeated peripheral reads. Every L PIB re-reads the physical device. A loop that scans 32 peripheral bytes burns 32 bus cycles, while a single L PID x plus a 4-byte T MD x consumes the same number of bytes with one bus transaction.
• PLC migration between S7 platforms. STL compiles to the same mnemonics across S7-300, S7-400, and S7-1500, but the environment differs. Re-import V5.x STL blocks into a TIA Portal V14+ project and recompile before field use; legacy STL opcodes (some early correlator / sequence instructions) are deprecated and trigger warnings on S7-1500.
• Real-number comparison after L. Loading a double-word real into ACCU 1 and immediately scanning with A reads only the low bit of the real’s binary image. Always use a typed comparison (L, L, >R, <R, etc.) for floating-point decisions.
• Re-entrancy of FB local data. L L 0.0 in an FB references the instance’s static buffer, not the DB opened globally with OPN DB. Make the L/T operand unambiguous by qualifying the variable name with the instance DB number on multi-instance FBs.
• Symbol-table vs absolute address. When the project imports an external STL source that uses absolute addresses, TIA Portal will not warn you on compile. Always inspect the generated compiler listing (“Project tree > Program blocks > Compile output”) to confirm the resolver mapped every absolute to the right symbolic tag.
• Force / unforce after the force table is closed. A forced bit continues to read “1” against A even after the table is closed. Clear forces explicitly with “Force table > Stop forcing” before relying on the live PLC state for diagnostics.
• STL and security. STL is a textual language, which makes it harder for a casual operator to “see” what the block does. Treat STL as security-sensitive: compile with knowledge protection enabled (“Block properties > Protection”) on any controller exposed to less-trusted networks.

Frequently Asked Questions