Simatic S5 Program Transfer: RAM vs EPROM Memory Guide

Simatic S5 Memory Architecture Overview

The Siemens SIMATIC S5 family stores the executable user program in three physically distinct media: volatile RAM backed by a buffer battery, UV-erasable EPROM memory submodules, and (on later CPU variants such as the S5-95U and S5-115U second-generation units) electrically erasable EEPROM. The CPU's onboard operating system (the Firmware AG and System Program) lives in a separate masked ROM and is not user-modifiable. Understanding which destination a STEP 5 download reaches is critical when commissioning, restoring after a soft-stop fault, or migrating programs between controllers.

When a STEP 5 Download command is issued from the programmer over the serial MPI/AS511 interface, the transfer target is determined by the active memory submodule physically present in the CPU's memory submodule slot, not by the STEP 5 software. Specifically:

• If a RAM submodule (e.g., 6ES5 375-0LA15, 6ES5 375-1LA15) is inserted, the program is written into volatile RAM and remains valid only while the buffer battery holds charge.
• If an EPROM submodule (e.g., 6ES5 372-1LA15, 6ES5 373-0LA15) is inserted, the CPU executes a copy operation that writes the program into the EPROM during the download. This requires that the EPROM be pre-erased and that no write-protection switch be engaged.

The SIMATIC S5 system manual STEP 5 / ST V7.1, Chapter 18.2 "Memory Submodules" documents this destination routing explicitly and is the canonical reference for any field engineer restoring an S5 system after a fault.

RAM, EPROM, and EEPROM Module Types

The three memory technologies are not interchangeable. Each has distinct electrical, mechanical, and operational characteristics that govern how the engineer must handle them.

The ceramic-windowed DIP EPROM package is unmistakable: a quartz window roughly 8 mm × 16 mm sits above the silicon die. This window must be covered with an opaque label during normal operation to prevent accidental erasure from ambient UV sources (notably fluorescent lighting and direct sunlight).

STEP 5 Program Transfer Targets

The STEP 5 programming software (versions V6.x through V7.2, with V7.1 the most widely deployed) issues a download via the menu path File > Download > Block or Transfer > EPROM. Two fundamentally different operations are available:

1. Standard Download (RAM) – The programmer writes the compiled blocks (OB, PB, FB, DB, SB, FX) directly to the CPU's RAM area via the AS511 serial protocol at 9600 bit/s. This is the default mode and is the operation the original poster performed after the overall reset.
2. EPROM Programming – This operation is available only when the external EPROM programmer connected to the PG is used, OR when a Siemens Field PG with an integrated submodule programmer is fitted. The CPU itself cannot erase or program a UV-EPROM; only a dedicated programmer can drive the Vpp (typically +12.5 V or +21 V) programming pulses required by the EPROM cell.

Overall Reset and Cold Restart Procedure

The scenario described in the source – a CPU that comes up in soft stop with the STOP LED flashing after a mechanical disturbance (dust ingress, reseating) – is a textbook case for the standard S5 recovery sequence. The IStack (Interrupt Stack) fault entries after such an event typically report errors in the DB 0 / DX 0 system data block, pointer corruption, or battery-fail flags.

1. Power down the central rack. Remove the CPU from the rack if the buffer battery shows any signs of leakage or low voltage.
2. Disconnect the buffer battery connector from the CPU front panel. This forces a true cold start and clears any RAM-resident pointer corruption that survived a warm restart.
3. Re-seat all memory submodules, I/O modules, and the CPU. Verify the slot coding keys match the hardware configuration.
4. Reconnect the battery only after the CPU has been powered on and reached STOP.
5. With the mode selector in STOP, perform an Overall Reset: hold the mode selector in the MRES position for 3 seconds, release, then rotate to MRES again within 3 seconds and hold for 3 seconds. The CR LED will flash twice to confirm.
6. Switch to RUN. The CPU will report an IStack fault if the program is missing or contains a syntax error – this is expected behavior.
7. Reconnect STEP 5, perform Transfer > Download to load the user program back into RAM.

Programming EPROM with Field PG M

The Siemens Field PG M (catalog number 6ES7 712-0AA00-0AA0 and successor part numbers 6ES7 712-1AA00-0AA0, 6ES7 713-1AA00-0AA0) integrates a submodule programmer directly into the PG chassis. The programming socket is located behind the front-panel cover and accepts 24-pin and 40-pin S5 memory submodules. The Field PG P (professional variant) and later Field PG M4 / M5 / M6 share the same programming electronics but use updated driver software (PROM programmers for STEP 5).

1. Insert the erased EPROM submodule into the programmer socket with pin 1 oriented toward the marking on the socket.
2. From STEP 5, select File > Transfer > EPROM (or use the integrated S5-EPROM Programmer utility under Start > SIMATIC > STEP 5 > Tools).
3. Choose the target file containing the compiled S5 program (.S5D project file or pre-compiled .BIN image).
4. Set the device selection to match the EPROM catalog number (e.g., 6ES5 372-1LA15 for 32 KB, 27C256-compatible).
5. Initiate programming. The programmer applies the Vpp voltage (12.5 V for standard EPROMs, 21 V for some 27C-series devices) and verifies each byte. Programming time for a full 32 KB EPROM is typically 60–90 seconds.
6. Remove the EPROM, cover the quartz window with the supplied opaque label, and install it in the CPU's memory submodule slot.

UV Erasure Procedure for EPROM Modules

UV-erasable EPROMs require exposure to short-wave ultraviolet light at a wavelength of approximately 253.7 nm for a cumulative dose of approximately 15 W·s/cm². Commercial EPROM erasers expose the device at 1 inch (≈ 25 mm) from a 12 mW/cm² lamp for 20 to 30 minutes.

1. Remove the EPROM from the CPU. Do not erase while installed – the UV will damage adjacent components and the quartz window will not be flush with the eraser lamp.
2. Place the EPROM in the eraser with the quartz window facing the UV lamp.
3. Set the timer for 25 minutes as a baseline; some EPROMs require 30+ minutes for full erasure of cells that have been programmed thousands of times.
4. After the cycle, read the EPROM back on the programmer and verify all bytes read 0xFF. Any non-FF byte indicates incomplete erasure.
5. Replace the opaque label on the window before storage or reinstallation.

UV erasure is a destructive, all-or-nothing operation. There is no way to erase a single block or byte; the entire device is cleared.

ISTACK Fault Interpretation After Dust-Ingress Events

The IStack (Interrupt Stack) is the CPU's internal diagnostic buffer that records the last fault condition before the CPU transitioned to STOP. Reading the IStack from STEP 5 via PLC > IStack is the first diagnostic step after any unexplained STOP. Common IStack entries following a mechanical disturbance such as the dust blow-out described in the source include:

A "STOP LED flashing" condition with the original poster's error pattern most commonly indicates a combination of pointer corruption and missing DBs – both of which are cleared by the overall reset + RAM re-download sequence they performed.

Memory Module Specifications and Part Numbers

The following are the most commonly encountered S5 memory submodules in legacy installations:

Compatibility between submodules and CPUs is strictly defined in the Siemens Industry Online Support portal under each CPU's product page. Substituting an EPROM for a RAM module (or vice versa) without an overall reset will result in a CPU that refuses to start, since the bootloader looks for different signatures.

Battery Backup and Volatile Memory Handling

RAM submodules retain their contents only while the buffer battery maintains a terminal voltage above approximately 3.0 V. The standard backup battery is the Siemens 6ES5 980-0AE11 (lithium) or equivalent third-party 3.6 V / 1.2 Ah primary cell. Battery life is typically 3–5 years at 25 °C; high ambient temperature dramatically reduces life.

When loading a program from EPROM to RAM, the procedure is:

1. Power down the CPU.
2. Insert the programmed EPROM submodule.
3. Hold the mode selector in MRES while powering up to force the bootloader to read from EPROM.
4. Power up. The bootloader copies EPROM contents into RAM.
5. The RAM backup battery retains the copy from this point onward.

Verification and Commissioning Checks

After any memory operation – download, EPROM programming, or overall reset – verify the system is healthy before returning it to service:

1. From STEP 5, perform PLC > Status and confirm the CPU reports RUN, no IStack faults, and the expected cycle time.
2. Use PLC > Force or PLC > Monitor to verify each block type is loaded: OBs, PBs, FBs, DBs, SBs, FXs.
3. Cross-check the program checksum against the source STEP 5 project file if an EPROM was used.
4. Perform a controlled I/O checkout, walking through each input and output in sequence.
5. Document the memory submodule catalog number, programmed date, and software revision in the maintenance log.

Troubleshooting Matrix

Frequently Asked Questions