Sizing Gate-Source Pull-Down Resistors in Half Bridges

Overview: What the Gate-to-Source Resistors Do

Typical application circuits for half-bridge gate driver ICs show a resistor connected from each MOSFET gate directly back to that MOSFET's source terminal - one across the high-side device (gate to floating source/switch node) and one across the low-side device (gate to power ground). They are not optional decoration. They perform three distinct jobs:

1. Guaranteed default OFF state. A MOSFET is off when V_GS = 0 V. The resistor forces the gate to track its own source whenever the driver output is not actively sourcing current - during power-up, after driver undervoltage lockout (UVLO), on a broken gate trace, or if the driver output goes high impedance.
2. Leakage bleed. The driver's low-side output leakage, plus MOSFET gate leakage and PCB surface leakage, has to develop a voltage somewhere. Without a defined DC path, that leakage charges the gate capacitance until the device begins to conduct.
3. Transient charge dump. During supply ramp-up, capacitive coupling (Miller charge through C_GD when the switch node moves) can inject charge into the gate. The resistor provides a passive, "brainless" discharge path that works before any control logic is alive.

Sizing Rule: Start From Driver Leakage

The resistor must be low enough that the worst-case leakage current cannot lift V_GS anywhere near the MOSFET threshold, and high enough that it does not waste drive current or dissipate significant power.

Upper bound (turn-off integrity):

R_pd(max) = V_GS(margin) / I_leak(max)

where:
  V_GS(margin) = a fraction of V_GS(th) minimum from the MOSFET datasheet
                 (a common engineering choice is 20-25% of V_GS(th,min))
  I_leak(max)  = driver output low-state leakage + MOSFET gate leakage
                 + estimated board/contamination leakage, at max Tj

Use the datasheet leakage figure for the driver's output in the LOW state if it is specified. If no such specification exists, the practical starting point is 47 kΩ and adjust from measurement. Note that both V_GS(th) and leakage currents degrade with temperature: threshold falls roughly a few mV/°C while leakage rises, so evaluate the ratio at maximum junction temperature, not at 25 °C.

Lower bound (drive efficiency and dissipation):

I_diverted = V_drive / R_pd            (steady-state current stolen from the driver)
P_R        = V_drive^2 / R_pd * D      (D = duty cycle the gate is held high)

Values are calculated from the formulas above for a 15 V gate drive; substitute your actual drive rail. Resistor power rating is rarely the limiting factor - drive-current diversion and bootstrap-capacitor droop usually are.

High-Side Specifics: Bootstrap Interaction

The high-side resistor connects gate to the floating source (switch node), so its current is drawn from the bootstrap capacitor while the high-side device is on. Two consequences:

• Bootstrap droop. The resistor discharges C_BOOT for the entire high-side on-time. Include this current when sizing the bootstrap capacitor: ΔV = (I_total × t_on(max)) / C_BOOT, where I_total includes quiescent current of the floating driver section, gate charge per cycle, and V_drive/R_pd. Keep ΔV well below the driver's high-side UVLO threshold.
• Layout. Return the resistor to the MOSFET source pin (or Kelvin source pad) at the device, not to a distant node. Any inductance shared with the power path injects V_GS noise that the resistor is supposed to suppress. Place the resistor and the gate resistor physically adjacent to the FET package.

Why You Cannot Use the Resistor as a Pull-Up for a Default-ON State

A tempting idea: if the required power-up state is high-side OFF and low-side ON, reconnect the low-side gate resistor to the +15 V rail instead of ground, so the low-side device conducts until the microcontroller finishes its boot sequence (which can be tens to hundreds of microseconds).

Do not do this. The pull-up and the series gate resistor form a permanent divider from +15 V to the driver output. When the driver pulls its low-side output (LO) to ground to turn the FET off, the gate does not reach 0 V - it settles at:

V_GS(off) = V_supply * R_gate / (R_gate + R_pullup)

Worked case (assumed values - substitute your own):
  V_supply = 15 V, R_gate = 10 ohm, R_pullup = 47 kohm
  V_GS(off) = 15 * 10 / 47010 = 3.2 mV        (negligible)

  But with R_gate = 2.2 kohm and R_pullup = 10 kohm:
  V_GS(off) = 15 * 2200 / 12200 = 2.7 V       (near or above V_GS(th))

The residual voltage depends entirely on the ratio, and it is worst exactly where designers use large series gate resistors for dv/dt control. Any residual V_GS near threshold means the low-side device is not fully off, so every high-side turn-on produces cross-conduction current. There is also a continuous DC path from +15 V through the driver output stage, and the pull-up fights the driver on every turn-off, slowing the turn-off edge and increasing switching loss.

Correct Ways to Define the Power-Up Bridge State

Note that the input-side pull-down/pull-up on HIN/LIN is a completely different network from the gate-source resistor and does not suffer the divider problem, because the driver's input impedance is high and its output stage still pulls the gate hard to the source.

Verification Procedure

1. Static leakage check. Power the driver bias rail with the control inputs held in the OFF state and the DC bus removed. Measure V_GS on both devices with a high-impedance (10 MΩ) probe. Anything above a few tens of millivolts means the resistor is too large for the actual leakage.
2. Hot check. Repeat at maximum expected ambient/heatsink temperature, where leakage is highest and V_GS(th) is lowest.
3. Power-up sequencing. With low DC bus voltage and a current-limited supply, scope both gate-source voltages differentially (isolated probe or differential probe for the high side) during bias ramp-up. Look for any transient V_GS excursion toward threshold. Include a fast rail rise and a slow, drooping rise.
4. Shoot-through screening. Monitor DC bus current with a current probe during switching. Current spikes coincident with the opposite device's turn-on edge indicate incomplete turn-off - check for stray gate voltage, insufficient dead time, or dv/dt-induced Miller turn-on.
5. Bootstrap validation. Measure the bootstrap capacitor voltage at maximum high-side on-time and confirm it stays above the high-side UVLO threshold with the pull-down current included.

Design Checklist

• Fit a gate-to-source resistor on every MOSFET in the bridge, referenced to that device's own source.
• Start at 47 kΩ when no driver leakage figure is available; reduce toward 10 kΩ for hot, high-leakage, or contaminated-environment designs.
• Verify R_pd × I_leak(max) is a small fraction of V_GS(th,min) at maximum junction temperature.
• Never return the pull-down to a positive rail to create a default-ON state.
• Add the pull-down current to the bootstrap capacitor budget for the high-side device.
• Keep the pull-down, the series gate resistor, and any gate-clamp components in a tight loop with the FET package.

FAQ