Wiring the S7-300 CPU 313C Integrated 24 DI: L+/M Groups and Pin 40 (3M) Reference
1. Overview of the CPU 313C Integrated I/O
The SIMATIC S7-300 CPU 313C is a compact CPU that combines a central processing unit with onboard digital and analog I/O. The integrated channel count is 24 DI / 16 DO digital and 4 AI / 2 AO analog, plus three integrated high-speed counters. Unlike the larger S7-300 CPUs that require separate signal modules (SMs) for every channel, the 313C carries these I/O directly on the CPU itself, terminated on a 40-pin front connector for the digital section and on a separate screw-terminal block for the analog section.
The 24 digital inputs are physically and electrically organised into three isolated groups of 8 inputs each. Each group has its own dedicated 24 V sensor supply terminal (L+) and its own ground return (M). The two output groups and the analog channels follow a similar grouping concept. The ground reference for one of these groups — the one commonly referred to in the field as the “third M rail” or 3M — is wired to pin 40 of the 40-pin front connector.
Getting L+ and M wrong on a 313C is one of the most frequent commissioning errors for engineers who are new to the compact CPU family, because the 40-pin connector on the CPU is laid out differently from the 20-pin connectors used on the standard SM-321 / SM-322 signal modules sitting next to it. The SMs are simple: one 20-pin connector, one L+, one M. The 313C front connector has the same physical form factor but carries four L+ rails and four M rails packed into a 40-pin footprint, with the analog I/O handled on a separate terminal block at the bottom of the CPU.
| CPU 313C variant | Order number (MLFB) | Integrated DI/DO | Integrated AI/AO | Counters |
|---|---|---|---|---|
| CPU 313C | 6ES7313-5BF03-0AB0 | 24 DI / 16 DO | 4 AI / 2 AO | 3 (10 kHz) |
| CPU 313C-2 DP | 6ES7313-6BF03-0AB0 | 24 DI / 16 DO | 4 AI / 2 AO | 3 (30 kHz) |
| CPU 313C-2 PtP | 6ES7313-6CF03-0AB0 | 24 DI / 16 DO | 4 AI / 2 AO | 3 (30 kHz) |
The wiring rules in this article apply to all three variants. The DP and PtP versions add a second interface (PROFIBUS-DP slave or serial PtP) but the integrated I/O terminal layout is identical.
2. Prerequisites and Reference Documentation
Before opening the front cover of the CPU, gather the following:
- S7-300 Automation System, CPU 31xC and CPU 31x Operating Instructions — Siemens entry ID 21866938. Figure 7-3 (terminal assignment of the integrated I/O on CPU 313C) is the canonical pinout reference.
- S7-300 CPU 31xC Technological Functions Manual — entry ID 109752420. Covers counters and the integrated I/O electrical data.
- S7-300 Module Data Reference Manual — entry ID 15343315, for diagnostic addresses and error LED behaviour.
- STEP 7 V5.5 / V5.6 with the hardware catalog updated to include CPU 313C firmware (the 313C ships with firmware V2.6 / V3.3 depending on MLFB; ensure the HSP matching the MLFB is installed).
- A 6ES7392-1AM00-0AA0 (screw-type) or 6ES7392-1BM01-0AA0 (spring-type) 40-pin front connector. Spring-type is recommended for vibration-prone cabinets.
- Ferrule-crimped conductors 0.25–1.5 mm² (24–16 AWG). Ferrules are mandatory on spring-type connectors.
- 24 V DC sensor supply, fused at 6–10 A, with a clean chassis earth at the M terminal.
3. CPU 313C Integrated I/O Architecture
The integrated I/O on the 313C is electrically and logically a set of four independent groups, each isolated up to 75 V DC from the CPU backplane and from each other:
| Group | Channels | Process image | Voltage | Type 1 / Type 3 (IEC 61131-2) |
|---|---|---|---|---|
| DI group 1 (8 DI) | I124.0 – I124.7 | IB 124 | 24 V DC | Type 1 (PNP, sourcing) |
| DI group 2 (8 DI) | I125.0 – I125.7 | IB 125 | 24 V DC | Type 1 (PNP, sourcing) |
| DI group 3 (8 DI) | I126.0 – I126.7 | IB 126 | 24 V DC | Type 1 (PNP, sourcing) |
| DO group 1 (8 DO) | Q124.0 – Q124.7 | QB 124 | 24 V DC, 0.5 A | Source (high-side switch) |
| DO group 2 (8 DO) | Q125.0 – Q125.7 | QB 125 | 24 V DC, 0.5 A | Source (high-side switch) |
| AI (4 channels) | PIW 752 / 754 / 756 / 758 | — | ±10 V, 0–10 V, 0/4–20 mA | Differential |
| AO (2 channels) | PQW 752 / 754 | — | ±10 V, 0–10 V, 0/4–20 mA | Single-ended |
All digital inputs are IEC 61131-2 Type 1: they source current into the input, so a positive 24 V signal applied to the input terminal with respect to the group's M terminal is read as a logical “1”. They are not Type 3 (TTL level) — applying 5 V will not be read reliably. The valid input voltage range is 15–30 V (nominal 24 V); the guaranteed “1” level is 15 V minimum and the guaranteed “0” level is 5 V maximum.
4. Front Connector Layout (Pin-by-Pin)
The CPU 313C ships with one 40-pin front connector. The analog I/O is on a separate removable terminal strip at the bottom of the CPU and is not part of the 40-pin connector. The figure below is the pinout that matches figure 7-3 of the S7-300 CPU 31xC Operating Instructions.
| Pin | Signal | Function | Group |
|---|---|---|---|
| 1 | 1L+ | 24 V supply, DI group 1 | DI 1 |
| 2 | I124.0 | Digital input bit 0 | DI 1 |
| 3 | I124.1 | Digital input bit 1 | DI 1 |
| 4 | I124.2 | Digital input bit 2 | DI 1 |
| 5 | I124.3 | Digital input bit 3 | DI 1 |
| 6 | I124.4 | Digital input bit 4 | DI 1 |
| 7 | I124.5 | Digital input bit 5 | DI 1 |
| 8 | I124.6 | Digital input bit 6 | DI 1 |
| 9 | I124.7 | Digital input bit 7 | DI 1 |
| 10 | 2L+ | 24 V supply, DI group 2 | DI 2 |
| 11 | I125.0 | Digital input bit 0 | DI 2 |
| 12 | I125.1 | Digital input bit 1 | DI 2 |
| 13 | I125.2 | Digital input bit 2 | DI 2 |
| 14 | I125.3 | Digital input bit 3 | DI 2 |
| 15 | I125.4 | Digital input bit 4 | DI 2 |
| 16 | I125.5 | Digital input bit 5 | DI 2 |
| 17 | I125.6 | Digital input bit 6 | DI 2 |
| 18 | I125.7 | Digital input bit 7 | DI 2 |
| 19 | 1M | Ground return, DI group 1 | DI 1 |
| 20 | 2M | Ground return, DI group 2 | DI 2 |
| 21 | 3L+ | 24 V supply, DI group 3 | DI 3 |
| 22 | I126.0 | Digital input bit 0 | DI 3 |
| 23 | I126.1 | Digital input bit 1 | DI 3 |
| 24 | I126.2 | Digital input bit 2 | DI 3 |
| 25 | I126.3 | Digital input bit 3 | DI 3 |
| 26 | I126.4 | Digital input bit 4 | DI 3 |
| 27 | I126.5 | Digital input bit 5 | DI 3 |
| 28 | I126.6 | Digital input bit 6 | DI 3 |
| 29 | I126.7 | Digital input bit 7 | DI 3 |
| 30 | 3M | Ground return, DI group 3 | DI 3 |
| 31 | 1L+ (DO) | 24 V load supply, DO group 1 | DO 1 |
| 32 | Q124.0 | Digital output bit 0 | DO 1 |
| 33 | Q124.1 | Digital output bit 1 | DO 1 |
| 34 | Q124.2 | Digital output bit 2 | DO 1 |
| 35 | Q124.3 | Digital output bit 3 | DO 1 |
| 36 | Q124.4 | Digital output bit 4 | DO 1 |
| 37 | Q124.5 | Digital output bit 5 | DO 1 |
| 38 | Q124.6 | Digital output bit 6 | DO 1 |
| 39 | Q124.7 | Digital output bit 7 | DO 1 |
| 40 | 1M (DO) / chassis earth tie-point | Ground return, DO group 1 (and field-referenced M for the analog section) | DO 1 / mixed |
5. Digital Input Grouping and L+/M Distribution
Three DI groups, each with its own power rail, allows mixed-voltage or mixed-grounded sensors in the same machine. Common field examples where the grouping matters:
- Galvanically isolated plant sections — group 1 reads signals from cabinet section A (M tied to ground A), group 2 reads signals from cabinet section B (M tied to ground B), avoiding a ground loop that would otherwise inject 50/60 Hz into the analog section.
- Different sensor supply PSUs — group 1 fed from PSU-A, group 2 from PSU-B, group 3 from a battery-backed UPS rail.
- Mixed PNP / NPN sensor field devices — only PNP (sourcing) sensors are supported on a Type 1 input; if any NPN (sinking) sensor must be wired, invert the supply on that group's L+/M (sensor's V+ on M, sensor's V− on L+) at the cost of breaking the IEC 61131-2 “1” level guarantee — a documented field workaround, not a Siemens-recommended configuration.
The 24 V sensor supply (L+ for each group) can be sourced from the same 24 VDC rail that feeds the CPU's power supply module (PS 305/PS 307), or from a separate dedicated sensor PSU. The M terminals of the three input groups are internally tied to the CPU's logic ground only through protection networks; each M must be bonded to the cabinet PE at exactly one point to avoid ground loops.
6. Pin 40 (3M) — The Critical Ground Reference
The 313C has four M rails, not three. The naming is the most common source of confusion:
| Pin | Label on connector diagram | Function | Reference impedance to PE |
|---|---|---|---|
| 19 | 1M | Ground return, DI group 1 | Functional earth (FE) |
| 20 | 2M | Ground return, DI group 2 | Functional earth (FE) |
| 30 | 3M | Ground return, DI group 3 | Functional earth (FE) |
| 40 | 1M (DO) — also called “4M” in some print versions | Ground return, DO group 1 and the analog M rail | Protective earth (PE), bonded internally |
Pin 40 is the M terminal that every other group of analog and counter I/O indirectly references through the isolated DC/DC converter on the CPU board. The practical advice is unambiguous: always terminate pin 40 to PE with the shortest possible conductor (≤ 100 mm, 2.5 mm² minimum, green/yellow sleeved). If pin 40 is left floating, the analog inputs show offset that drifts with temperature, the high-speed counters miscount the first 1–3 pulses after a STOP→RUN transition, and the SF LED can come on intermittently with a diagnostic buffer entry of 0x0001 (“module fault”) that clears on the next warm restart.
Field engineers often describe pin 40 as “3M” because the third input-side M terminal is the one most often mistaken for an unused pin when only the first 8 inputs of group 1 are wired. The manual's figure 7-3 labels the pins unambiguously; the on-sticker label inside the front cover shows the same pin numbers but in a different visual layout (rows of 10 instead of 20). When in doubt, read the wiring diagram printed inside the cover, not the legend on the connector housing.
7. Pre-Wiring Safety and Tools Required
- Isolate the 24 VDC supply feeding the CPU and the sensor PSUs. Lock-out / tag-out per local electrical safety procedure (EN 60204-1 / NFPA 70E).
- Verify zero energy with a calibrated multimeter at the L+ and M terminals of every group.
- Open the CPU front cover by pressing the release lever at the bottom of the cover.
- Loosen the two Pozidriv-2 screws at the top and bottom of the front connector; the connector unplugs by pulling straight out.
- Strip each conductor to 8 mm, crimp a ferrule (DIN 46228 E1.5-8 or equivalent), and verify the crimp with a pull test (≥ 30 N for 0.5 mm²).
- Use a Pozidriv-1 (screw-type) or the spring-actuation tool (spring-type) screwdriver. Torque screw-type terminals to 0.4–0.7 N·m (Siemens 6ES7392-1AM00-0AA0 spec).
8. Step-by-Step Wiring Procedure for Group 1 (8 DI)
The user case is to wire the first 8 digital inputs (I124.0 – I124.7) of the CPU 313C and leave the analog section unconnected. Proceed as follows.
- Identify the 1L+ and 1M pins. Pin 1 (1L+) supplies the sensor rail. Pin 19 (1M) is the ground return. Both are referenced to the bottom row of the 40-pin front connector. The on-cover sticker shows these two pins as the “leftmost supply pair” of the connector's first row of 10 pins.
- Land 1L+ on pin 1. Run a red 1.0 mm² conductor from the fused 24 VDC sensor bus to pin 1. If the field is not yet ready, leave pin 1 unterminated and put a ferrule on the conductor for strain relief — pin 1 is not a no-connect.
- Land 1M on pin 19. Run a blue 1.0 mm² conductor from the 24 VDC supply's 0 V rail to pin 19. Bond this 0 V rail to PE at the PSU end only — do not also bond pin 19 to PE locally, otherwise you create a ground loop with the analog section.
- Wire the eight inputs to pins 2–9. Each input is wired between the sensor's 24 V signal output and the input pin. The sensor's 0 V / GND is tied to the same 0 V rail as pin 19. Eight black conductors, 0.5 mm², ferrule-crimped.
- Wire pin 40. Land a green/yellow 2.5 mm² PE conductor on pin 40. Connect the other end to the cabinet PE bar with the shortest possible path (≤ 100 mm). This single connection is what makes the integrated analog and counter I/O quiet in noisy cabinets.
- Leave groups 2, 3, and the DO group unwired for this exercise. The unused L+ pins (10, 21, 31) and M pins (20, 30, 40 already landed) can be left open, but the ungrounded M pins of the unused groups must be tied to the cabinet 0 V rail to prevent the group from floating into an undefined state on CPU start-up.
- Verify continuity with a buzzer or low-current ohmmeter between pin 1 and the 24 VDC bus, between pin 19 and the 0 V rail, and between pin 40 and the PE bar. Resistance should be < 0.5 Ω end-to-end on each.
- Re-install the front connector with the two retaining screws torqued to 0.6 N·m. Close the front cover.
9. Extending to the Remaining DI Groups and the DO Module
The user confirms that the second integrated module (a standard SM-323 or SM-322 in slot 2 of the rack) is already wired. To complete the 24 DI, the remaining wiring is:
| Group | L+ pin | M pin | Input pins | Source PSU (recommended) |
|---|---|---|---|---|
| DI group 1 (CPU) | 1 | 19 | 2–9 (I124.0–I124.7) | PSU-A (24 VDC sensor bus 1) |
| DI group 2 (CPU) | 10 | 20 | 11–18 (I125.0–I125.7) | PSU-A or PSU-B (your choice) |
| DI group 3 (CPU) | 21 | 30 | 22–29 (I126.0–I126.7) | PSU-B (24 VDC sensor bus 2) |
| SM-321 / SM-323 (slot 2) | per SM pinout | per SM pinout | per SM pinout | per local engineering standard |
| DO group 1 (CPU) | 31 | 40 | 32–39 (Q124.0–Q124.7) | 24 VDC load PSU |
For a mixed-source architecture (group 1 from PSU-A, group 2 from PSU-B), the two PSU 0 V rails must be tied together at exactly one point — typically at the main distribution block — so the input optocouplers of the CPU see a common reference. If the two PSUs are truly isolated and the field design requires galvanic isolation between two plant sections, leave the 0 V rails separate and accept that the corresponding M pins (19 vs 20) are also separate — this is the intended use of the grouped design.
10. Analog I/O Wiring (4 AI / 2 AO) Considerations
The four analog inputs (PIW 752, 754, 756, 758) and two analog outputs (PQW 752, 754) are wired to the removable terminal strip at the bottom of the CPU, not the 40-pin front connector. Wire each channel as a shielded twisted pair with the shield bonded to PE at the cabinet entry, not at the field-device end, to avoid ground-loop currents in the shield.
The measuring range is set in STEP 7 under HW Config → CPU 313C → Analog Inputs → Properties → Inputs, with the choices ±10 V, 0–10 V, 1–5 V, 0/4–20 mA. Channels are differential inputs; for current measurement, a 250 Ω precision resistor (Vishay Z201 or equivalent) must be wired across the + and − terminals of each channel used in current mode. This resistor is not internal to the 313C.
Unused analog channels must be shorted + to − at the terminal strip and configured as “deactivated” in HW Config, otherwise the channel can show random full-scale values and trigger a wire-break diagnostic (0x0010 in the diagnostic buffer).
11. STEP 7 Hardware Configuration and Commissioning
After mechanical wiring, commission the CPU in the following sequence:
- Open SIMATIC Manager → your S7 project → HW Config.
- Insert the CPU 313C (order number matching the MLFB on the front panel) into slot 2 of rack 0. STEP 7 will populate the integrated I/O automatically with the default addresses 124–126 (DI/DO) and 752–759 (AI/AO).
- Right-click the CPU → Object Properties → Integrated I/O. Verify that the DI, DO, AI, and AO sub-modules are enabled. Deactivate unused AI channels to suppress wire-break diagnostics.
- Right-click the AI sub-module → Properties → Addresses. Note the start address 752. This must match the wiring labels on the terminal strip; re-mapping is rarely required.
- Set the input filter on each DI group: 0.1 ms (fast, for high-speed counters), 0.5 ms, 3 ms (default), or 15 ms (for noisy field wiring). On CPU 313C this is a per-CPU setting, not per-channel.
- Save and compile the HW Config; download to the CPU (target system → CPU 313C → download).
- Go online and force IB 124 in the VAT (Variable Table). All eight input bits should read 0 with the sensor leads open; touching 24 V to I124.0 should toggle bit 0 to 1.
For high-speed counter use, switch the relevant inputs to the “Count” function in HW Config (CPU 313C has three counters using inputs I124.0/I124.1, I124.2/I124.3, and I124.4/I124.5 by default). The function assignment is exclusive — a digital input used as a counter pulse cannot be used as a standard process input simultaneously.
12. Verification and Commissioning Checklist
| Step | Action | Pass criterion |
|---|---|---|
| V1 | Measure L+ to M voltage at pins 1 / 19 with CPU powered | 24 VDC ±10 % (21.6–26.4 V) |
| V2 | Measure pin 40 to PE | < 1 Ω (bond integrity) |
| V3 | Force IB 124 = 0, drive I124.0 high externally | Bit 0 transitions to 1 within 1 OB1 cycle (≤ 10 ms) |
| V4 | Force IB 125 and IB 126 in the same way | All 24 bits toggle |
| V5 | Set QB 124 to 0xFF, measure pin 32 to pin 40 | 24 VDC on each Q124.x with respect to pin 40 |
| V6 | Check CPU diagnostic buffer for entries after a 10-minute run | No I/O fault entries (0x00E1 / 0x00E2 / 0x0010) |
| V7 | Monitor the SF LED | Off; a red SF on a freshly-wired 313C almost always indicates a missing pin-40 bond |
| V8 | Trigger a STOP → RUN transition | No “module fault” entry; high-speed counters start from 0 |
13. Troubleshooting Matrix
| Symptom | Likely cause | Diagnostic step | Fix |
|---|---|---|---|
| All 24 DI read 0 even with 24 V applied | 1L+ (pin 1) not powered or 1M (pin 19) floating | Measure pin 1 to pin 19 | Restore 24 VDC; bond pin 19 to PSU 0 V |
| Group 1 reads but groups 2 and 3 do not | 2L+ (pin 10) or 3L+ (pin 21) missing; 2M (20) or 3M (30) floating | Measure pin 10–20 and 21–30 | Wire the missing L+/M pairs; the diagnostic buffer will not flag a missing L+ on the CPU 313C, only a missing M will set SF |
| Analog inputs drift by 0.5–2 LSB with temperature | Pin 40 not bonded to PE | Measure pin 40 to PE bar; should be < 1 Ω | Add the 2.5 mm² PE bond; the 24-bit Σ-Δ stage inside the analog section references PE through pin 40 |
| SF LED on, diagnostic buffer shows 0x00E1 | I/O access error to integrated module | Check PLC → Module Information → Diagnostic Interrupt | Confirm the front connector is fully seated; check the two retaining screws are torqued to 0.6 N·m |
| High-speed counter undercounts first 1–3 pulses after STOP→RUN | Pin 40 floating or bonded to PE through a long (> 0.5 m) conductor | Measure inductance of the pin 40 bond (should be negligible) | Shorten the pin 40 conductor; the 30 kHz counter stage of the 313C-2 is sensitive to common-mode noise on the M return |
| Input intermittently toggles 0↔1 without sensor change | Loose ferrule or solder-tinned conductor end | Visual + pull test on the terminal screw | Re-crimp with a fresh ferrule; re-torque to 0.6 N·m |
| One channel of a group reads but the other seven do not | That single input terminal is loose; the M terminal of the group is fine | Continuity check pin 2 to the sensor wire | Re-crimp the affected input only; the other seven will continue working because the M terminal is shared and intact |
| All DI read 1 even with 0 V applied | 1M (pin 19) tied to +24 V instead of 0 V | Measure pin 19 to PSU 0 V; should be 0 V | Correct the wiring; reverse polarity on the M terminal can damage the input optocouplers if sustained for > 1 hour |
| Output group 1 will not energise load | DO 1L+ (pin 31) missing or 1M DO (pin 40) floating | Measure pin 31 to pin 40 under load | Restore 24 VDC to pin 31; verify pin 40 PE bond |
14. Common Field Pitfalls Specific to CPU 313C
- Confusing the 40-pin CPU connector with a 20-pin SM connector. The 313C ships with a 40-pin connector. An SM-321 / SM-322 uses a 20-pin connector. Do not try to seat a 20-pin connector into the 313C's 40-pin header — the keying is different and you will bend pins.
- Leaving unused M pins floating. Unlike the SM-321, the CPU 313C integrated inputs do not have internal M bonds between groups. Every group M (1M, 2M, 3M) must be physically wired to 0 V, even if no sensor is connected to that group.
- Bonding pin 40 at both ends. Pin 40 is PE-referenced at the CPU's internal DC/DC converter. If you also bond it locally to the cabinet PE bar and run it to the analog section's 0 V, you create a 50/60 Hz loop that the analog channels will pick up. Choose one: PE at the cabinet, or 0 V at the analog section, never both.
- Reading the front-cover sticker as the wiring diagram. The sticker is a layout reminder; the wiring diagram is in the manual (figure 7-3) and on the inside of the front cover when the cover is opened. The two are not identical visually.
- Skipping the input filter configuration. The default 3 ms filter is appropriate for general-purpose digital inputs but is too slow for the high-speed counter inputs (which expect 0.1 ms). Configure the filter explicitly in HW Config, not by hardware RC debouncing at the terminal.
15. Frequently Asked Questions
Where exactly do I land L+ and M for the first 8 digital inputs of the CPU 313C?
L+ for DI group 1 is pin 1 of the 40-pin front connector; M (ground return) for the same group is pin 19. The eight input bits I124.0 – I124.7 land on pins 2 through 9. The sensor's 24 V output goes to the input pin, and the sensor's 0 V returns to pin 19.
What is pin 40 on the CPU 313C, and why is it called “3M” in some field references?
Pin 40 is the M (ground) terminal for DO group 1 and the consolidated low-impedance return for the isolated analog and counter sections. Field engineers sometimes call it “3M” or “4M” because the third input-side M (pin 30) is the one most often mistaken for an unused terminal when only the first eight inputs are wired. Wire pin 40 to PE with a ≤ 100 mm, 2.5 mm² green/yellow conductor for clean analog readings.
Can I leave the analog I/O (4 AI / 2 AO) of the CPU 313C completely unwired?
Yes, the analog section can be left unconnected, but you must deactivate the unused AI channels in HW Config (right-click the AI sub-module → Properties → uncheck the “Enabled” box for each unused channel). Otherwise, an unconnected channel triggers a wire-break diagnostic entry 0x0010 and the SF LED will illuminate.
Why does the SF LED come on even though all my digital inputs are wired correctly?
The three most common causes on a CPU 313C are: (1) pin 40 not bonded to PE, (2) one or more group M terminals (pins 19, 20, 30) left floating, and (3) a loose front connector. Measure the resistance from each M pin to your 0 V bus and from pin 40 to the PE bar; both should read < 1 Ω.
Do I need to use a special 40-pin connector for the CPU 313C, or can I reuse a 20-pin SM connector?
You must use a 40-pin front connector (Siemens 6ES7392-1AM00-0AA0 screw-type or 6ES7392-1BM01-0AA0 spring-type). The 20-pin connector used on the SM-321/SM-322/SM-323 modules will not seat on the CPU's 40-pin header and attempting to force it will bend pins. The CPU ships with one 40-pin connector in the box; spares are ordered separately.
What is the default STEP 7 address for the integrated 24 DI on a CPU 313C?
The default addresses are IB 124, IB 125, IB 126 — three bytes, one per input group. The corresponding bit addresses are I124.0 – I124.7 (group 1), I125.0 – I125.7 (group 2), and I126.0 – I126.7 (group 3). These addresses can be re-mapped in HW Config if required to avoid conflicts with the SM I/O sitting next to the CPU.