Configuring DP/DP Couplers with Redundant S7-400H Systems

Adding a Siemens 6ES7 158-0AD01-0XA0 DP/DP Coupler to a redundant S7-400H pair is a common integration task when a third-party controller, a separate H-station, or a remote PROFIBUS segment must exchange process data with both CPUs. The challenge is not electrical or protocol-level — both DP/DP couplers will handshake on PROFIBUS-DP without issue — but is a STEP 7 engineering constraint: STEP 7 HW Config will not allow two slave devices on the same PROFIBUS subnet to share an identical PROFIBUS address. Because redundancy in an H-system implies logical equivalence of the two CPUs and their attached slaves, this conflict must be resolved in the application program rather than at the configuration layer.

This reference covers the architecture, the address-conflict root cause, the active-CPU detection mechanism, the dual-write/single-read I/O strategy, and the diagnostic verification steps required to bring up a DP/DP-coupled redundant H-station. Sample STEP 7 V5.x STL/SCL code is provided for SFB/FC blocks and H-status bits, with parallel notes for users migrating to STEP 7 TIA Portal.

1. Reference Architecture

The baseline topology that motivates this article is shown below. Two redundant CPU 417-4H (or 414-4H / 416-4H) controllers form the S7-400H station, each with its own PROFIBUS-DP interface (IF1 or an IF964-DP plug-in). A 315F safety PLC and an ET200M remote I/O station are already on the same DP subnet. The new requirement is to add a DP/DP Coupler on each H-CPU so that two independent PROFIBUS segments can be cross-coupled without sharing a bus.

Key design intent:

• Both 400H CPUs must be able to send the same process outputs to the third-party controller in case of an H-switchover.
• The third-party controller must be able to send inputs to one of the two H-CPUs at a time — the currently-master CPU.
• PROFIBUS addresses on the third-party side could be identical (3 and 3) if it were not for the STEP 7 constraint described below.

2. DP/DP Coupler Fundamentals

The DP/DP Coupler (order number 6ES7 158-0AD01-0XA0, successor 6ES7 158-0AD02-0XA0) connects two PROFIBUS-DP networks as a router. Up to 16 bytes of input data and 16 bytes of output data can be transferred in each direction; the coupler is configured on each side independently with the same maximum data length. The device supports PROFIBUS baud rates from 9.6 kbit/s to 12 Mbit/s and is transparent to DP-V0 and DP-V1 services when those services are not used in the I/O image area.

Electrical and protocol characteristics relevant to H-system use:

For H-system integration, the coupler is treated as a standard DP slave — STEP 7 has no awareness of redundancy, and the GSD does not declare any redundancy-related diagnostics. The redundancy must therefore be implemented in the application program.

3. Why STEP 7 Blocks Identical PROFIBUS Addresses

PROFIBUS-DP uses the slave address to:

1. Address parameterisation and configuration telegrams during start-up.
2. Resolve data exchange (DX) and read/write (RW) requests from the master.
3. Identify the source of diagnostic interrupts.

Two slaves with the same address on a single bus segment would both respond to the same request, and the master would be unable to associate the response with a single slave. STEP 7 enforces uniqueness at configuration time, not at runtime: when you drag a second instance of the DP/DP Coupler GSD into HW Config and assign it the same PROFIBUS address as the first, the editor rejects the assignment with:

Error: Address X is already assigned to another station on subnet 'PROFIBUS(1)'.

The address slot is reusable from the field device's perspective — physically both couplers behave correctly if both were assigned address 3, because the H-system has only one active DP master on the bus at any moment and the inactive side does not poll its coupler. STEP 7 cannot model this "runtime exclusivity" because it sees a single static subnet configuration.

Three practical workarounds are used in the field:

For the remainder of this article, the third (application-level) method is developed in detail because it is the only one that survives a Y-link constraint: a Y-link cannot be used when the two DP/DP couplers must each talk to a different higher-level redundant controller, which is the scenario described in the field report.

4. Detecting the Active H-CPU

An S7-400H pair exposes the role of each CPU through standard system bits and through system functions. The most reliable signal in STEP 7 V5.x is the master/reserve status bit readable from the system data area of the H-CPU.

4.1 Status bits in the system data

The H-system status word contains a set of bits maintained by the redundancy firmware:

These bits are accessible via the standard system data byte OB1_START_INFO (in OB1), and the same data is available in the system status word (SZL) list when read with SFC 51 (RDSYSST) using SZL-ID W#16#0131 (H-CPU status information, index 0).

4.2 Reading the status with SFC 51

// STL — Read H-system status into a marker word
CALL  SFC  51             // RDSYSST
     REQ    := TRUE
     SZL_ID := W#16#0131  // H-CPU status
     INDEX  := W#16#0000
     RET_VAL:= MW 100     // Return code
     BUSY   := M 102.0
     SZL_HEADER := MD 104 // SZL header (length info)
     DR     := MW 110     // 16-bit status word

The returned 16-bit word at MW 110 has the layout described in the table above. Bit 0 is the MasterCPU flag for the CPU that executed the call.

4.3 Equivalently: SFB 52 / SFB 54 in TIA Portal

In TIA Portal, the same information is exposed as the system tag <CPU name>.HSystem.SlaveActive (or via the GETIO_PART / SETIO_PART instructions). The mapping is:

// SCL (TIA Portal V16 or later) — read H role
IF "HSystem".MasterActive THEN
   // this CPU is the master, use its DP/DP input area
   // ... copy inputs from process image to work DB
ELSE
   // this CPU is the reserve, ignore input area
END_IF;

5. Master/Reserve Switching Logic

With the role of each CPU known, the application program must implement two functions:

1. Output multiplexer (dual-write): Both H-CPUs write the same output data to their respective DP/DP couplers. The third-party controller reads whichever side is online; if it is itself redundant it can use the dual inputs as its own redundancy source.
2. Input demultiplexer (single-read): The third-party controller writes its output to the DP/DP coupler that is currently talking to the master H-CPU. The reserve H-CPU must ignore the input area of its own DP/DP coupler.

This is the "write to both output areas at the same time, but just read one CPU at a time" pattern described in the field report, and it is the standard pattern for any H-to-singular-DP-slave link.

6. Dual-Write, Single-Read I/O Strategy

6.1 Output handling — dual-write

Outputs are written to both DP/DP couplers unconditionally. Because only the master H-CPU's PROFIBUS interface is actively polling its coupler, the reserve CPU's writes are queued in the process image and have no effect on the bus — which is exactly what is wanted.

// STL — Dual write to both DP/DP couplers (PEP: 0..15 bytes per direction)
// Assume the DP/DP couplers occupy:
//   PEW 200 .. PEW 215 on CPU0 (input from 3rd party)
//   PEW 300 .. PEW 315 on CPU1 (input from 3rd party)
//   PAW 200 .. PAW 215 on CPU0 (output to 3rd party)
//   PAW 300 .. PAW 315 on CPU1 (output to 3rd party)
// Outputs are identical and taken from shared DB "DB_H_DP".

L   DBW  0          // output word 0 from shared DB
T   PAW  200        // to DP/DP #1 (CPU0)
T   PAW  300        // to DP/DP #2 (CPU1)

L   DBW  2
T   PAW  202
T   PAW  302
// ... repeat for the configured I/O length

6.2 Input handling — single-read with edge latch

// STL — Input multiplexer (single-read)
// On master CPU: copy input words to shared DB.
// On reserve CPU: zero / hold last value (do not overwrite).

A   M  110.0        // MasterCPU bit from SFC 51
FP  M  120.0        // rising-edge latch (avoid race)
JC  CPY_IN

// reserve CPU path
L   0
T   DBW  10         // input word 0 to shared DB (held / zeroed)
JU  END_IN

CPY_IN: NOP 0
L   PEW  200        // only CPU0 sees active data; CPU1's PEW 300 is irrelevant
T   DBW  10
L   PEW  202
T   DBW  12
// ... repeat for the configured I/O length
END_IN: NOP 0

7. Hardware Configuration in STEP 7 HW Config

7.1 Inserting the DP/DP couplers

1. Open the S7-400H station in HW Config. Open properties of the DP interface (X2 or X3, depending on your slot). Confirm the operating mode of the interface is "DP master" — the H-CPU is the master on its own subnet, the DP/DP couplers are slaves.
2. Open the PROFIBUS subnet catalog. Right-click the DP master interface and choose "Insert Object → PROFIBUS-DP Slave". Browse to PROFIBUS DP → Additional Field Devices → Gateway → DP/DP Coupler. Add two instances.
3. Assign PROFIBUS address 3 to the first instance and 4 to the second. If you attempt to use the same address, HW Config will refuse with the duplicate-address error.
4. Open the slot configuration of each instance. Set the I/O length to match the third-party controller's data length (1 to 16 bytes in each direction). The slot must be the same on both couplers — input length N at the first slot, output length N at the slot 1 position — to keep the parameterisation symmetrical.
5. Save and compile (Station → Save and Compile). The diagnostic buffer of each CPU should be free of configuration errors.

7.2 GSD handling

If the third-party controller's PROFIBUS master requires a vendor-specific GSD, install it via Options → Install GSD File in HW Config or Options → Device Repository in TIA Portal. The DP/DP coupler ships with SIEM8171.GSD; later firmware variants may ship SIEM8171C.GSD — confirm against the readme on the device's support page before deployment.

7.3 Sync constraints between the two H-CPUs

For the dual-write / single-read pattern to remain consistent across an H-switchover, the application DB used to share I/O data between the two CPUs must be either:

• declared as a mixed DB where output words are written redundantly by the application and input words are written by the master only, or
• separated into two DBs: one for outputs (written by both CPUs, read by both), and one for inputs (written by the master, read by both).

Whichever layout is used, the DBs must be in the H-system's non-synchronised area, otherwise the firmware will copy them at the same rate and the input demultiplex will fight the master-change.

8. Sample STL/SCL Code for Active CPU Detection

8.1 SCL version (STEP 7 V5.5 / SCL)

FUNCTION FC 1001 : VOID
VAR_TEMP
   ret     : INT;
   busy    : BOOL;
   hdr     : DWORD;
   status  : WORD;
END_VAR
BEGIN
   // Read H-system status from SZL 0x0131
   RDSYSST(REQ := TRUE,
           SZL_ID := W#16#0131,
           INDEX := W#16#0000,
           RET_VAL := ret,
           BUSY := busy,
           SZL_HEADER := hdr,
           DR := status);

   IF ret = 0 AND NOT busy THEN
      // Bit 0 = MasterActive, Bit 1 = ReserveActive, Bit 2 = RoleChange
      "db_status".masterActive := status.%X0;
      "db_status".reserveActive := status.%X1;
      "db_status".roleChange := status.%X2;
   END_IF;
END_FUNCTION

8.2 Where to call it

• OB 1 (main): acceptable for slow processes (> 50 ms cycle).
• OB 35 (cyclic interrupt, 100 ms): recommended; the status word is refreshed every cycle independent of OB1 scan time.
• OB 72 (CPU redundancy error): use to latch the master-change event and trigger an audit log entry.

9. Verification and Diagnostics

9.1 Start-up checks

1. Both DP/DP couplers power up — ON and RDY LEDs steady green.
2. BF1 on the H-side DP/DP coupler is OFF for the master CPU; the same LED on the reserve side may flash briefly during link-up but must be OFF in steady state.
3. STEP 7 online: PLC → Monitor/Modify on the shared output DB. Set a value of 0xAAAA at the first output word. Confirm with the third-party controller's diagnostic tool that the value is received on both DP/DP coupler addresses (3 and 4).
4. Force an H-switchover (CPU STOP on the master). Within one OB1 cycle, the reserve CPU takes the master role. The MasterChange bit is high for one cycle. The third-party controller's input data continues to flow from address 3 or 4 — the application code automatically switches the source.

9.2 Online diagnostics in STEP 7

Open PLC → Accessible Nodes, select each H-CPU, and check the diagnostic buffer for SFC/SFB errors and DP slave diagnostics. Useful entries:

9.3 DP/DP coupler LED behaviour

10. Alternative: Y-Link — Why It Is Not Suitable Here

The Y-Link (6ES7 197-1LA04) is the official Siemens component for connecting a redundant DP master system to a non-redundant PROFIBUS slave segment. It performs a master/reserve switchover internally, presenting a single DP master to the lower-level slaves and using both H-CPUs as redundant masters upstream.

However, the Y-link works only when the two redundant masters on the upper side are a single S7-400H station, and the slaves on the lower side are one non-redundant DP segment. The topology in this article has the opposite requirement: two separate PROFIBUS subnets on the H-side (one per DP/DP coupler) must communicate with two separate controllers on the third-party side. The Y-link is therefore not a viable replacement.

If the third-party side were a single non-redundant controller and the requirement were simply "talk to either of two H-CPUs transparently", a Y-link on the H-side would be the correct solution.

11. Troubleshooting Matrix

12. Migration to TIA Portal

For S7-400H stations that are migrated to TIA Portal (V15 or later with the H option package), the configuration is functionally identical but the mechanism to read the master/reserve status is different. The relevant data block is generated automatically by the TIA Portal H wizard and is found at PLC tags → System constants → HSystem. The system constant exposes the following members:

The dual-write / single-read code from Section 6 is portable directly to TIA Portal with the substitution of MasterActive for the SFC 51 result bit.

13. Field-Proven Caveats

• Shared DB sync: If the shared DB used to exchange I/O between the two H-CPUs is in the H-sync area, do not write the same byte from both CPUs in the same cycle — the firmware will report a non-fatal discrepancy and may log a sync error. Mark the DB as non-synchronised in the H parameters (HW Config → CPU → Properties → H Parameters → Synchronisation → Exclude from link-up).
• DP/DP coupler firmware: Older coupler firmware revisions (V1.x) do not support DP-V1 services. If your third-party controller uses DP-V1 class 1/2 acyclics, confirm the coupler firmware is V2.0 or later (printed on the device label, or read via the diagnostics page if the higher-level system supports it).
• Cable length and baud rate: The two PROFIBUS subnets are independent. Each can run at a different baud rate up to 12 Mbit/s. The DP/DP coupler adapts transparently. Do not exceed the PROFIBUS segment length budget for the chosen baud rate on either side.
• Hot-swapping the reserve CPU: During a planned hot-swap of the reserve CPU (rack removed), the master's DP/DP coupler continues to operate normally. There is no need to disable the reserve CPU's DP/DP coupler explicitly — its outputs are not on the bus while the CPU is in STOP / removed.
• Time stamping of inputs: If the third-party controller relies on the H-CPU's time stamp for inputs (e.g. for sequence-of-events recording), the time stamp on the reserve CPU's PEW will be the time of last read, not the time the data arrived. Only use the master CPU's PEW for time-stamping; this is automatic if the demultiplex is applied before the time-stamping FC.

14. Related Configuration Items

• IF964-DP — plug-in PROFIBUS-DP interface for the H-CPU. Required if the integrated DP port is used for the Y-link or for ET200M and a second DP port is needed for the DP/DP coupler. Order number 6ES7964-2AA04-0AB0.
• Synchronisation cable (fibre-optic) — required between the two H-CPUs for redundancy. Order number depends on the distance (1 m, 2 m, 10 m variants). See the S7-400H system manual for the part-number table.
• PROFIBUS connector — 6ES7972-0BA12-0XA0 (90° cable outlet) or 6ES7972-0BB12-0XA0 (35° cable outlet) for the DP/DP coupler side. Each connector must be terminated if it sits at the end of the segment.

FAQ