Configuring Multiple Cyclic Interrupts on Siemens S7-300/400 CPUs

Overview: Why You Cannot Always Add Another Cyclic Interrupt

Siemens SIMATIC S7-300 and S7-400 CPUs execute cyclic interrupt OBs in the OB30 to OB38 range. The default is OB35 set to 100 ms, and most S7-300 CPUs ship with OB35 already inserted in the offline program. When a programmer right-clicks the S7 program container in SIMATIC Manager and inserts an additional block such as OB36, the editor accepts the new block and the symbol table parses cleanly, but the download to the target CPU terminates with a system error: "The OB is not supported by the target CPU" or "Download of OB36 to CPU 314C-2 PN/DP not possible". The error is not a project bug, it is a hardware/firmware constraint: many CPU 31x variants only support one cyclic interrupt OB in their run-time system, while S7-400 CPUs and the newer S7-31x PN/DP and CPU 319 family support multiple OBs simultaneously.

Two paths solve the problem:

1. Native multi-OB configuration when the CPU hardware/firmware allows it. Configure OB30, OB31, OB32, OB33, OB34, OB36, OB37, OB38 from HW Config > CPU Properties > Cyclic Interrupts.
2. Multiplexer workaround for CPUs that allow only one cyclic OB. Run OB35 (or whichever OB the CPU permits) at the fastest supported interval, count the calls in a marker word, and use STL MOD arithmetic to dispatch sub-tasks at 100 ms, 150 ms, 200 ms, 1 s, or any integer multiple of the base interval.

Prerequisites

• SIMATIC STEP 7 V5.5 SP2 or later (works on V5.4 SP3 and V5.3 SP3 with identical STL syntax).
• SIMATIC Manager with the appropriate CPU HSP (Hardware Support Package) installed for the target CPU.
• Target CPU type and firmware version known. Identify via HW Config > PLC > Module Information, or read MLFB from the module label.
• Online connection via MPI, PROFIBUS, or Ethernet (CP 343-1 / CP 443-1) for download and verification.
• Working knowledge of STL accumulator operations or willingness to use the SCL equivalent.

Cyclic Interrupt OB Numbering and Default Behaviour

All S7-300/400 CPUs share the same OB numbering for cyclic interrupts:

OB35 with a 100 ms interval is the factory default for S7-300 CPUs. The interval can be modified from 1 ms to 60 000 ms in HW Config, but most CPU 31x variants enforce a minimum of 10 ms and reject values below that range during HW Config download.

Identifying Which Cyclic OBs Your CPU Supports

The fastest way to determine hardware support is the hardware configuration:

1. Open HW Config in SIMATIC Manager.
2. Double-click the CPU module (rack slot 2 or 3).
3. Select the Cyclic Interrupts tab.
4. Inspect the OB column. CPUs that support only one OB show a single entry (OB35). CPUs that support multiple OBs list OB30 through OB38 with editable Execution, Phase Offset, and Priority fields.

Use the table below as a quick reference for common S7-300/400 CPU families. Always cross-check against the printed manual for your specific MLFB and firmware version.

If your CPU shows only OB35 with an uneditable count, you are in the multiplexer territory. The download error you saw in the offline > online transfer dialog is the firmware enforcing this exact limitation.

Native Multi-OB Configuration (When Supported)

For S7-400 CPUs, CPU 319-3, and S7-1500 controllers configured in TIA Portal, multiple cyclic OBs are first-class citizens.

1. Open HW Config and double-click the CPU.
2. Open the Cyclic Interrupts tab.
3. Click the row for the OB you want to enable (for example OB36) and tick Enabled.
4. Set Execution to the desired interval, for example 200 ms.
5. Set Phase Offset to stagger the start time relative to OB35. A 50 ms offset on OB36 with a 200 ms interval guarantees OB36 fires 50 ms after OB35 each cycle and avoids overlapping scan spikes.
6. Set the OB Priority. Priorities 9 to 12 are typical for cyclic interrupts on S7-400. Higher priority OBs can preempt lower ones.
7. Save, compile, and download HW Config first, then download the program blocks.

The Multiplexer Workaround: One Fast OB, Many Effective Intervals

When the CPU only allows one cyclic OB, configure that OB at the fastest interval the CPU permits (typically 10 ms on CPU 314, 1 ms on CPU 315-2 PN/DP and higher). Inside the OB, maintain a free-running counter in a marker word (MW, DBW, or static variable in an FB). For each desired effective interval, test whether the counter modulo the integer ratio equals zero, and if so, jump to the sub-task body. This is the canonical STEP 7 V5.5 STL pattern.

Why It Works

OB35 fires every T ms (for example 10 ms). The counter MW0 increments by 1 on every entry, so it counts elapsed OB invocations. The condition (MW0 MOD N) == 0 is true on every Nth entry, which corresponds to an effective interval of N × T ms. With T = 10 ms and N = 10, the effective interval is 100 ms; with N = 15 it is 150 ms; with N = 100 it is 1 000 ms. Because the dispatcher lives in the only cyclic OB, all sub-tasks are mutually time-serialised and never overlap, which simplifies priority management on the PLC side.

STL Code Walkthrough

The reference STL is written in pure STEP 7 V5.5 syntax. All instructions are documented in the SIMATIC STEP 7 V5.5 Statement List (STL) for S7-300 and S7-400 Programming manual, Section 7 "Integer Math Instructions".

//----------------------------------------------------------
//  OB35 — Multiplexed cyclic dispatcher
//  Base interval: 10 ms (configured in HW Config)
//  MW0 = free-running call counter
//----------------------------------------------------------

      L     MW0                       // Load counter
      +    1                          // ACCU1 = ACCU1 + 1
      T     MW0                       // Store counter

//------ Effective 100 ms task (ratio = 10) ------
      L     MW0
      L     10                        // 100 ms / 10 ms = 10
      MOD                            // ACCU1 = MW0 MOD 10
      L     0
      ==I                            // ACCU2 == 0 ?
      JC    int1                      // Jump to 100 ms block

//------ Effective 150 ms task (ratio = 15) ------
      L     MW0
      L     15                        // 150 ms / 10 ms = 15
      MOD
      L     0
      ==I
      JC    int2                      // Jump to 150 ms block

//------ Effective 1 s task (ratio = 100) ------
      L     MW0
      L     100                       // 1000 ms / 10 ms = 100
      MOD
      L     0
      ==I
      JC    int3                      // Jump to 1 s block

      JU    endOB                     // Skip sub-task bodies

int1:                               // Begin 100 ms body
      // ... call FB / set outputs / read inputs ...
      JU    endOB

int2:                               // Begin 150 ms body
      // ... 150 ms logic ...
      JU    endOB

int3:                               // Begin 1 s body
      // ... 1 s logic ...
      JU    endOB

endOB: BEA                           // Block end

Why the +1, T, MOD, ==I, JC Pattern

The same logic expressed in SCL is more compact:

// SCL version — place inside OB35
#iCnt := #iCnt + 1;

IF (#iCnt MOD 10) = 0 THEN
    // 100 ms body
END_IF;

IF (#iCnt MOD 15) = 0 THEN
    // 150 ms body
END_IF;

IF (#iCnt MOD 100) = 0 THEN
    // 1 s body
END_IF;

IF #iCnt > 32000 THEN
    #iCnt := 0;    // wrap to avoid overflow on INT range
END_IF;

Step-by-Step Implementation in SIMATIC Manager

1. Open the project in SIMATIC Manager and confirm the target CPU's MLFB and firmware version match the prerequisite table.
2. Open HW Config, double-click the CPU, select the Cyclic Interrupts tab, and confirm OB35 is the only enabled entry. Set OB35 to the fastest interval the CPU permits (commonly 10 ms).
3. Save and download HW Config first. The PLC must accept the new OB35 interval before the program is downloaded.
4. Open OB35 in the program editor (LAD/FBD/STL/SCL).
5. Add the counter increment (L MW0 / +1 / T MW0) at the top of OB35.
6. Add one MOD / ==I / JC block per desired effective interval. Use unique jump labels (int1, int2, int3, ...) and finish each sub-task body with JU endOB to skip the remaining bodies.
7. Append endOB: BEA at the very end of OB35 to mark the block end.
8. Compile the S7 program (F7 or via menu). The compiler reports the OB size in the local data; ensure the OB does not exceed the CPU's local data stack (default 256 bytes per priority class, configurable in HW Config > Memory).
9. Download to the target CPU. The download should now succeed because you are reusing the existing OB35 rather than adding a new OB36.
10. Go online and open a VAT (Variable Table) to monitor MW0. Confirm MW0 increments by 1 every 10 ms, that MW0 MOD 10 = 0 is true exactly once per 100 ms, and that the 150 ms / 1 s branches also fire as expected.

Verification Procedure

1. Create a VAT with the tag MW0 and the status display format set to DEC. The value should climb 1, 2, 3, ... once per OB execution.
2. Add a second tag for the 100 ms body execution counter (e.g. MW10) and increment it inside the int1 block. The online trend should show a 10:1 ratio between MW0 and MW10.
3. Use Monitor/Modify on a digital output wired to a panel lamp or scope. Toggle the output inside each sub-task body. With a 100 ms effective interval and a 50% duty cycle, the lamp should appear solidly lit at 5 Hz on a scope.
4. Check PLC > Diagnostic Buffer for OB35 priority class overruns. A "OB35 cycle time exceeded" or "OB35 priority class error" entry indicates that the total execution time of all sub-tasks is longer than the 10 ms base interval. Either raise the base interval or split the bodies into multiple OBs once the CPU firmware allows it.
5. Force a STOP/RUN transition and confirm MW0 starts from 0 (or from the retained value, depending on whether MW0 is set to Retain in the symbol table). For deterministic behaviour, force a reset of MW0 in OB100 (warm restart) or in the startup OB of the CPU.

Edge Cases, Jitter, and Caveats

Alternative: Time-of-Day and Hardware Interrupts

Where cyclic OB multiplexing still does not give the deterministic phase required, combine the multiplexer with one of the following:

• Time-of-day interrupts OB10-OB17: configured in HW Config > CPU Properties > Time-of-Day Interrupts. Up to 8 start times, each can fire daily, weekly, monthly, or on the last day of the month. Use for hard real-time calendar tasks (shift reports, end-of-day routines).
• Hardware interrupts OB40-OB47: triggered by digital input edges, CP interrupts, or FM module events. Use for low-latency, event-driven response where cyclic scan is too slow.
• SFB35/SFB36/SFB37 (ALARM_8P, NOTIFY_8P, ALARM_8): diagnostic interrupts generated from the user program. Useful for status polling at intervals that are independent of the cyclic OB.

Comparison: Native Multi-OB vs Multiplexer

Migrating to TIA Portal / S7-1500

If your application can move to S7-1200/1500 with TIA Portal V16 or later, the multiplexer is no longer required. Add multiple cyclic interrupt OBs from Program Blocks > Add New Block > Organization Block > Cyclic Interrupt, and TIA Portal presents a wizard that lets you pick the interval and phase offset for each OB. The S7-1500 CPU 1516-3 PN/DP supports sub-millisecond intervals (500 µs minimum on most variants), and the S7-1200 G2 manual collection confirms that the family supports up to 20 cyclic interrupt events in total. The TIA Portal V18 release notes also introduce Synchronous Actions in cyclic OBs for motion control integration.

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