CPU 1513-1AL02 Firmware V2.6: Resolving TIA V13 HSP Missing

Problem Overview

Engineers migrating a Siemens S7-1500 station from the older CPU 1513 (order number 6ES7 513-1AL00-0AB0) to the newer CPU 1513 (order number 6ES7 513-1AL02-0AB0) frequently encounter two coupled defects inside TIA Portal V13 SP1 Update 9. The first defect is that the new CPU and its firmware V2.6 do not appear in the hardware catalog even after a catalog update. The second defect is that the system memory byte (typically MB0) and the clock memory byte (typically MB1) remain inactive on the replacement CPU, producing no system-edge transitions and no oscillating clock bits for the user program.

Both symptoms share a common root cause: TIA Portal V13 SP1 is older than the firmware generation supplied by the 6ES7 513-1AL02-0AB0, and the system/clock memory bytes require explicit enabling in the CPU properties followed by a hardware configuration download. The procedures and field-proven caveats below resolve both issues without replacing the project or rolling back the firmware.

CPU 1513 Hardware Identification: Catalog Number Reference

Siemens assigns a unique MLFB (Machine-Readable Product Designation) to every CPU variant. The two MLFBs in this scenario differ only in the two-digit version suffix, but the suffix governs the firmware generation and the engineering toolchain required to configure the device.

The 6ES7 513-1AL02-0AB0 is fully back-compatible at the application program level, but TIA Portal versions prior to V15.1 cannot install the corresponding Hardware Support Package (HSP) for firmware V2.6. The catalog update feature inside V13 SP1 UPD 9 cannot bridge this gap because the HSP is gated by the engineering tool version, not by the catalog metadata.

TIA Portal Version Compatibility Matrix for S7-1500 Firmware V2.6

Siemens publishes a strict version matrix that ties the S7-1500 firmware generation to the TIA Portal engineering tool generation. Engineers must match the tool version to the target firmware generation before initiating a CPU replacement; otherwise the device will not appear in the hardware catalog regardless of catalog refresh attempts.

The version relationship is non-linear. TIA Portal V15 introduced firmware V2.5, but V2.6 was deliberately reserved for the V15.1 release line. Engineers who attempt to add the V2.6 HSP through the Options > Support Packages dialog inside V13 SP1 will observe that the package is either greyed out or simply absent from the installed packages list.

Hardware Support Package (HSP) Architecture in TIA Portal

Siemens distributes device descriptions for newly released CPUs as compressed HSPs that are separate from the TIA Portal installer media. Each HSP contains:

• The device description (GSD-equivalent for PROFINET and PROFIBus)
• The icon and catalog tree entry for the TIA Portal hardware catalog
• The firmware-image metadata required to identify the CPU during a device replacement
• The faceplate and HMI tag definitions for the integrated display where applicable

The HSP does not contain the firmware binary itself. Firmware is delivered separately as a .upd file via the Siemens Industry Online Support portal and is loaded into the CPU using the SIMATIC Automation Tool, the TIA Portal online & diagnostics view, or a micro memory card. This separation allows Siemens to add CPU support without re-releasing the full TIA Portal DVD image.

Inside the TIA Portal installation directory the HSPs reside under:

Each HSP folder contains a HwcnExp.xml manifest, the localized catalog text, and the device bitmap set. When a TIA Portal version is older than the firmware generation, the HSP simply does not exist on the Siemens support server for that tool version, and no amount of catalog refresh will retrieve it.

Step-by-Step HSP Installation Procedure

Use the following procedure inside the target TIA Portal version to install a Hardware Support Package. The same procedure is documented in the TIA Portal Help under "Options > Support Packages" and applies to TIA Portal V14 through V18.

1. Download the appropriate HSP file (for example HSP_TIA_V15_1_HWUpdate_xxx.zip) from the Siemens Industry Online Support portal. The HSP must match the TIA Portal major version line. Do not attempt to load a V15.1 HSP into V13 SP1; the installer will reject the package with an "incompatible manifest" error.
2. Close all running TIA Portal instances. The Support Packages installer requires exclusive access to the catalog database.
3. Launch the TIA Portal version that matches the HSP. From the main menu, select Options > Support Packages. The Support Packages dialog opens.
4. In the dialog, ensure the "Installation of support packages" option is selected. This is the default entry in the left-hand navigation pane.
5. Click "Add" (the file-folder icon) and navigate to the downloaded .zip HSP file. The dialog displays the contained HSPs and their target firmware versions.
6. Select the checkbox next to each HSP you intend to install. Multiple HSPs from the same archive can be selected in one pass.
7. Click "Install". The installer extracts the package, validates the manifest, and registers the new devices in the TIA Portal catalog database. A green status indicator confirms success; a red indicator lists the offending manifest lines.
8. Restart TIA Portal when prompted. The new CPU entries (including the 6ES7 513-1AL02-0AB0 with firmware V2.6) now appear in the hardware catalog under PLC > SIMATIC S7-1500 > CPU.
9. Refresh the hardware catalog by right-clicking the catalog root and selecting "Update Catalog", or by pressing F5.

System Memory Byte (MB0) and Clock Memory Byte (MB1) Configuration

Siemens S7-1500 CPUs expose two special memory areas that the user program can poll without any explicit configuration in the program code: the system memory byte and the clock memory byte. Both areas are disabled by default in the CPU properties. The user reported symptom — MB0 and MB1 "always not active" — is the expected default state, not a defect in the CPU or the project.

System Memory Byte (MB0) Bit Assignments

The system memory byte provides one bit per predefined CPU status event. The following table lists the standard bit assignments for the S7-1500 system memory byte. The byte address is selectable in the CPU properties (any free MB address is acceptable; the convention is MB0).

Clock Memory Byte (MB1) Frequency Assignments

The clock memory byte toggles its bits at eight independent frequencies. The frequencies scale with the CPU scan cycle and are CPU-typical rather than wall-clock fixed. The convention is MB1 with the standard frequency set.

Enabling System and Clock Memory Bytes

1. Open the project in TIA Portal and select the CPU device in the project tree.
2. Open Properties > System and clock memory from the inspector window.
3. Check the box "Enable the use of system memory byte" and enter the byte address. The Siemens convention is MB0; the address is user-selectable but must not collide with process I/O or retentive data.
4. Check the box "Enable the use of clock memory byte" and enter the byte address. The Siemens convention is MB1.
5. Confirm with OK. The properties are now staged in the hardware configuration.
6. Compile the hardware configuration, then download the hardware configuration to the CPU. A program download is not sufficient; the system/clock memory enable flag is a hardware-configuration property, not a software-block property.
7. After the download, perform a STOP-to-RUN transition (or warm restart) on the CPU. The system memory byte bit assignments and the clock memory byte frequency oscillator start on the next scan cycle.

Hardware Configuration Download and Verification

Once the system and clock memory bytes are enabled in the CPU properties, the new configuration must be transferred to the physical CPU and the CPU must be restarted for the changes to take effect. The verification sequence is as follows.

1. Connect the engineering station to the CPU over PROFINET or PROFIBus and establish an online connection in TIA Portal.
2. Select the CPU in the project tree and choose Online > Download to device > Hardware configuration (or Download to device > Software and hardware configuration if the software blocks have also changed).
3. Confirm the target device and the PG/PC interface. TIA Portal displays the device comparison dialog when the offline configuration differs from the online configuration.
4. Check the boxes for the system memory byte and clock memory byte enable flags in the comparison dialog. These two entries are typically listed under the CPU properties subtree.
5. Click Download. The CPU receives the new configuration and, depending on the option selected, may go to STOP and back to RUN automatically.
6. After the download completes, force the CPU into STOP, then back to RUN, to ensure the system memory byte edge "First cycle" (MB0.0) fires exactly once.
7. Add a watch table to verify. Enter the addresses MB0 and MB1 in the watch table and observe:

MB0 = 0x0F   // Bit 0 = 1 (first cycle just fired), Bit 1 = 1, Bit 2 = 1, Bit 3 = 1
MB1 = oscillating // Bits toggle at their assigned frequencies

Bit 2 of the system memory byte is hard-wired to TRUE and bit 3 is hard-wired to FALSE, which is the fastest possible verification: if MB0.2 is TRUE and MB0.3 is FALSE, the system memory byte is active. If MB1 toggles at any frequency, the clock memory byte is active.

Migration Path: Upgrading from TIA V13 SP1 to TIA V15.1 or Later

Because the firmware V2.6 HSP exists only in TIA Portal V15.1 and later, a project currently authored in V13 SP1 must be migrated. The migration does not require rewriting the user program; TIA Portal preserves S7-1500 block code across version upgrades. The recommended migration sequence is:

1. On the engineering station, install TIA Portal V15.1 (or the latest patch level) side by side with the existing V13 SP1 installation. Siemens supports parallel installations of different TIA Portal major versions on the same workstation.
2. Archive the existing V13 SP1 project using Project > Archive. The resulting .zap13 archive is the migration source.
3. Open TIA Portal V15.1 and select Project > Retrieve. Point the dialog at the .zap13 archive. TIA Portal V15.1 converts the project to its internal format and reports any blocks or devices that require manual review.
4. After the conversion, open the device configuration. The 6ES7 513-1AL02-0AB0 now appears in the hardware catalog under PLC > SIMATIC S7-1500 > CPU with firmware V2.6 available.
5. Perform a device replacement: right-click the existing 6ES7 513-1AL00-0AB0 in the device view, choose Change device > CPU 1513 (6ES7 513-1AL02-0AB0), and accept the device comparison. TIA Portal maps I/O addresses, PROFINET device names, and program blocks automatically.
6. Enable the system memory byte (MB0) and clock memory byte (MB1) in the new CPU's properties as described in the previous section.
7. Compile, download, and verify.

Common Pitfalls and Field-Proven Caveats

The following pitfalls have been observed in field deployments of the CPU 1513-1AL02-0AB0 on TIA Portal V13 SP1 and are documented here to shorten the diagnostic cycle.

1. Catalog refresh performed in V13 SP1 after firmware V2.6 release. The V13 SP1 catalog server does not host the V2.6 HSP. The refresh completes successfully but adds no new devices. Engineers who rely on catalog refresh alone will wait indefinitely for V2.6 support to appear.
2. HSP installed under the wrong TIA Portal version. Each HSP is bound to a single TIA Portal major version. Installing a V15.1 HSP into V15.0 produces an "incompatible package" error and rolls back the install. Verify the TIA Portal version in the title bar before opening the Support Packages dialog.
3. System and clock memory bytes enabled in project but not downloaded. The CPU firmware only honors the enable flags after a hardware configuration download and a STOP-to-RUN transition. Saving the project without downloading is a common source of "the bytes are still zero" complaints.
4. System memory byte address collision with retentive data. If MB0 is also configured as a retentive byte in the PLC tags, the system memory bits will be overwritten on every warm restart. Select a byte that is not in the retentive range.
5. Clock memory frequency dependent on scan cycle. The clock memory byte frequencies are CPU-typical, not wall-clock fixed. A heavily loaded CPU may stretch the periods. If precise timing is required, use a hardware timer or a periodic OB instead of the clock memory byte.
6. Device replacement preserves program but resets IP address. The device replacement from 6ES7 513-1AL00-0AB0 to 6ES7 513-1AL02-0AB0 carries the PROFINET device name and IP configuration from the offline project. If the replacement CPU is online during the replacement, the new CPU takes the IP address only after the download; until then it retains the factory default IP 0.0.0.0.
7. Firmware update requires separate .upd file. Installing the HSP does not change the firmware on the physical CPU. The CPU continues to run whatever firmware was flashed at the factory until a firmware update .upd file is loaded via the SIMATIC Automation Tool, the TIA Portal online & diagnostics view, or a micro memory card.

Diagnostic and Troubleshooting Matrix

Verification Checklist

After applying the steps above, the following checklist confirms a successful resolution. Complete every item before returning the station to production.

• TIA Portal version is V15.1 or later, matching the V2.6 HSP generation.
• The 6ES7 513-1AL02-0AB0 appears in the hardware catalog under PLC > SIMATIC S7-1500 > CPU with firmware V2.6 as a selectable variant.
• The device replacement from 6ES7 513-1AL00-0AB0 to 6ES7 513-1AL02-0AB0 completed without unresolved differences in the device comparison dialog.
• The system memory byte is enabled at the documented address (MB0) and the clock memory byte is enabled at MB1.
• The hardware configuration was compiled successfully and downloaded to the CPU.
• The CPU was forced to STOP and then back to RUN after the download.
• A watch table confirms MB0 = 0x0F immediately after the STOP-to-RUN transition (first cycle bit set).
• A watch table confirms MB1 bits toggle at their assigned frequencies within 12.8 seconds of the RUN transition.
• The user program polls the new system/clock memory bits without modification (the SCL/ST/LAD code that referenced MB0 and MB1 on the old CPU continues to work unchanged).
• The physical CPU firmware version, read from the CPU display or the online & diagnostics view, matches the firmware configured in the offline project.

Related Reference Material

The following Siemens Industry Online Support resources are the authoritative source for the procedures documented above. Use them to verify package versions, firmware download files, and migration notes specific to your installation.

• Siemens Industry Online Support — TIA Portal version overview and download index
• Siemens TIA Portal Help — Installing the Hardware Support Package (HSP)
• Siemens Industry Online Support — SIMATIC S7-1500 CPU 1513 manual entry

FAQ