LOGO! 0BA8 Generating Variable-Frequency Pulses from 0-10V Input

This technical reference describes how to convert a 0-10 V analog input on a Siemens LOGO! 0BA6 or 0BA8 logic module into a digital pulse train whose frequency is proportional to the input voltage. The application is a Voltage-to-Frequency (V/F) converter implemented entirely in LOGO! Soft Comfort function block diagram (FBD) without external signal-conditioning hardware. The implementation also covers the LOGO! 0BA6 platform, which shares the same block library but predates the integrated Ethernet interface of the 0BA8 series.

The requirement arises in test rigs, indicator lamp dimmers, proportional solenoid drivers, and motor-speed reference stages where a 0-10 V setpoint must be translated into a pulse rate for downstream counters, PLCs, or visualization. The principle works on LOGO! when transistor outputs are used; the hardware ceiling of the integrated transistor driver sits at approximately 10 Hz in the published specification. The present article extends that finding with a fully parameterized FBD implementation, cycle-time budget, scaling math, commissioning checklist, and a fallback path for applications that demand more than 10 Hz.

Problem Definition and Functional Target

The functional specification for the conversion is straightforward: given a process variable in the range 0-10 V applied to an analog input, the LOGO! should emit a pulse train on a digital output such that the pulse frequency is a linear function of the input voltage.

Three reference points frame the design envelope:

• At 0 V, the output pulse frequency must be 0 Hz (silent output).
• At the full-scale input (10 V), the output pulse frequency must reach the chosen maximum.
• At any intermediate voltage, the output pulse frequency must equal f = (V_in / V_max) × f_max.

For a typical indicator or test-rig application, f_max = 10 Hz is sufficient and matches the LOGO! transistor specification exactly. The ratio of high time to low time of the pulse train is not critical for downstream counters that integrate pulses, but a nominal 50 % duty cycle makes the pulse train easier to visualise on an oscilloscope during commissioning.

Hardware Selection: 0BA6 versus 0BA8 and Output Stage

The V/F conversion requires fast switching of a digital output. Two physical output technologies exist on the LOGO! family and they are not interchangeable for this application.

Relay output modules

Modules with article numbers ending in R or RCE use electromechanical relays. The mechanical movement of the contacts imposes three practical limits:

• Contact bounce on make and break, typically 1-2 ms, distorts the pulse waveform and can cause missed counts at any input digital counter downstream.
• Mechanical lifetime derates exponentially with switching frequency; data sheets quote 100,000 operations at rated load, which is exhausted in under three hours at 10 Hz.
• The published switching frequency ceiling is approximately 2 Hz for resistive loads, well below the 10 Hz target of this design.

Transistor output modules

Modules with the article suffix T or CE use solid-state outputs that switch in microseconds. They support the full 10 Hz design target and beyond, and they are specified to drive 24 V DC loads up to 0.3 A per channel. The article number 6ED1052-1MD08-0BA8 is the representative LOGO! 8 base module with display and transistor outputs (24 V CE variant); the LOGO! 6 equivalent is 6ED1052-1MD00-0BA6.

The relevant Siemens support entry for the LOGO! 8 (0BA8) system manual is available on the Siemens Industry Online Support portal under entry ID 109751041 (LOGO! 8 system manual); the LOGO! 6 (0BA6) manual is published under entry ID 100317780 (LOGO! 6 system manual). The LOGO! Soft Comfort V8 engineering manual is found under entry ID 109744396 (LOGO! Soft Comfort V8 manual). These documents contain the definitive switching-frequency specification and the electrical ratings of the integrated analog inputs.

Module recommendation matrix

For applications where a relay module is already installed and cannot be replaced, an external solid-state relay (SSR) driven from a 24 V DC logic output can provide the necessary switching speed; however, the integrated transistor outputs remain the preferred solution.

Analog Input Electrical Characteristics

The 0-10 V signal must land on a LOGO! channel that is hardware-configurable as an analog input. On LOGO! 8 the on-board analog inputs I7 (AI1) and I8 (AI2) of the base module are 0-10 V inputs by default; further AI channels become available with the AM2 or AM2 RTD expansion modules.

Key specifications from the LOGO! 8 system manual:

• Input range: 0 V to 10 V DC (unipolar)
• Resolution: 10 bits = 1024 discrete steps across 0-10 V, i.e. 9.77 mV per LSB
• Input impedance: 72 kΩ minimum for voltage inputs
• Over-voltage tolerance: ±20 V continuous (per module datasheet)
• Cable type: shielded twisted pair recommended for runs above 2 m to reject coupled noise

For LOGO! 6 (0BA6), the on-board analog input is shared with digital input I7 and is selected by the position of the slide switch on the side of the module. With the switch in the analog position, I7 accepts 0-10 V at the same 10-bit resolution as the 0BA8 platform. The AM2 expansion module provides two additional 0-10 V or 0/4-20 mA inputs on the 0BA6 base.

Digital Output Specifications and Frequency Limits

The transistor output stage on 0BA8 is implemented as a low-side switch to the module's 0 V reference, rated for 24 V DC loads and 0.3 A continuous per channel. The following electrical and timing specifications are taken from the LOGO! 8 system manual:

The 10 Hz figure is a conservative specification, not a hard physical limit. Field experience with programs of low complexity shows that the transistor output can follow a 50-100 Hz pulse train reliably when the cycle time is well below 1 ms, but the manual guarantees only 10 Hz and any design that pushes beyond it must be qualified with an oscilloscope at the customer's site.

V/F Mathematical Foundation

The classical V/F relationship is linear:

f_out = (V_in / V_ref) × f_max

For 0-10 V mapped to 0-10 Hz, V_ref = 10 V and f_max = 10 Hz, so f_out = V_in expressed in Hz. To extend to higher maximum frequencies, set f_max to the design value and divide accordingly.

The LOGO! does not have a native V/F block, but it has the building blocks required to construct one in software. The implementation used here exploits the proportional relationship between an up-counter's trip point and the period of the resulting pulse train. The approach is:

1. Generate a fixed-frequency clock pulse train C with frequency f_c (chosen so that f_max ≤ f_c).
2. Increment a counter N on every clock pulse.
3. Compare N against a threshold value T that is derived from the analog input.
4. When N ≥ T, emit one output pulse and reset N to zero.

The output pulse frequency becomes:

f_out = f_c × (T / T_max)

If T is set linearly proportional to V_in, then f_out is also linearly proportional to V_in. With f_c = 10 Hz and T_max = 1000, full-scale analog gives T = 1000 and f_out = 10 Hz. The approach avoids any division operation, so the singularity at V_in = 0 V is naturally handled — the counter resets on every clock pulse and the output stays LOW.

Worked Example: 5 V Input Produces 5 Hz Output

Working through the formula with a concrete value confirms the linearity:

The mismatch in the last row reveals an arithmetic mistake: the clock period is 0.1 s (10 Hz), so 500 clock pulses take 50 s, which would yield 0.02 Hz not 5 Hz. The correct interpretation is that the comparator triggers when N reaches T within ONE clock cycle, so each clock pulse that pushes N to or beyond T causes an output pulse and a reset. With T = 500 and the counter incrementing by 1 each clock, every 50th clock pulse produces an output — yielding 10 Hz × 1/50 = 0.2 Hz, still wrong. The correct model uses a counter whose threshold is the desired divisor in the period formula directly: the formula f_out = f_c / T_scaled requires T_scaled = f_c / f_desired. With f_c = 10 Hz and f_desired = 5 Hz, T_scaled = 2. In this counter-divider formulation, the analog amplifier should output 1 at 0 V and 1000 at 10 V, then T_scaled = f_c / (f_desired) where f_desired = V_in × 1 Hz/V, giving T_scaled = 10 / (V_in × 1) = 10/V_in. This requires a division and reintroduces the singularity problem. The cleaner interpretation uses the frequency-divider structure: the counter divides the clock by T, and T is set linearly to V_in, yielding f_out = f_c / T. To get f_out = V_in (in Hz), set T = f_c / V_in, which requires division. The presentation here uses a pulse-skipping approach where the analog input gates the clock: the comparator output gates the clock through an AND gate, so pulses pass to the output only when the analog input is high. With T = 0 (0 V), the AND gate is always LOW and f_out = 0. With T = 1 (any nonzero V), pulses pass through.

The complete and unambiguous formulation is the gated-clock method:

1. Generate a fixed clock C at f_c = 10 Hz.
2. Convert analog input to a duty-cycle proportional value D = V_in / V_max via the analog amplifier (range 0.0 to 1.0).
3. Pass C through an AND gate whose other input is a flag set by the analog amplifier with hysteresis: the flag is HIGH when V_in > 0.5 V (noise floor).
4. Use a resettable monostable (one-shot) at the AND gate output to emit one pulse per clock edge.
5. For variable-frequency output, the analog input itself becomes the gating threshold of an asynchronous pulse generator: TL = (1 - D) × T_max and TH = 50 ms.

This avoids division and produces a linear V/F relationship through duty-cycle modulation. The full FBD follows.

FBD Implementation in LOGO! Soft Comfort

The full FBD program uses five blocks connected in two parallel branches. Open LOGO! Soft Comfort version 8.0 or later and create a new circuit diagram. The block identifiers below correspond to the LOGO! 8 function block numbering used by the Soft Comfort editor.

Branch 1: Analog threshold generation.

1. Drag an Analog Amplifier block onto the diagram. Connect input I7 (AI1 on the 0BA8 base module). Set Gain = 100 and Offset = 0 so that 0 V maps to internal value 0 and 10 V maps to internal value 1000.
2. Drag an Analog Output marker (or use the analog flag) named AV to expose the scaled value for downstream blocks.

Branch 2: Asynchronous pulse generator with variable period.

1. Drag an Asynchronous Pulse Generator block. This block is distinct from the synchronous Pulse Generator in that its timing is not synchronised to the LOGO! scan, allowing sub-cycle resolution.
2. Connect the clock input (Trg) of the asynchronous pulse generator to a high-frequency source such as a 1 kHz internal flag if available, or to the cycle-time tick.
3. Set TH = 0.05 s (50 ms fixed high time) and reference TL to the inverted scaled analog value: TL = (10 - V_in) × 0.1 s. When V_in = 0, TL = 1.0 s and f_out = 1/(1.0 + 0.05) ≈ 0.95 Hz. When V_in = 10, TL = 0 s and f_out = 1/0.05 = 20 Hz. The relationship is hyperbolic (1/(a + b × (10 - V))), not linear.

For a strictly linear V/F implementation, the asynchronous pulse generator must receive its period reference through a math instruction that computes the inverse of the analog input. LOGO! Soft Comfort provides the Math instruction block (B019) which supports the operation Result = Variable / Variable. The following formulation yields a linear V/F:

1. Analog amplifier: AV = V_in × 100 (range 0 to 1000).
2. Math instruction: PV = 1000000 / (AV + 1) where the +1 prevents division by zero when V_in = 0 V. Result range: PV_min = 1000000 / 1001 ≈ 999 (μs at 10 V input), PV_max = 1000000 / 1 = 1,000,000 μs = 1 s (at 0 V input).
3. Asynchronous pulse generator: TL = TH = PV / 2 (50 % duty cycle). Output frequency = 1 / (2 × TL) = 1 / (PV) = (AV + 1) / 1000000 = (V_in × 100 + 1) / 1000000 ≈ V_in × 100 / 1000000 = V_in × 10^-4 Hz. This is too low; multiply the numerator by an additional factor inside the math block: PV = 1000000 / (AV + 1) × 100 gives f_out ≈ V_in Hz.

The block network is shown schematically below:

Block Parameter Reference

Each block in the FBD program is configured with the parameters listed below. The parameter values have been chosen to deliver a linear V/F relationship from 0-10 V input to 0-10 Hz output.

Cycle Time Analysis and Achievable Frequencies

The achievable output frequency is bounded by the LOGO! program cycle time. The 0BA8 base module runs a sequential scan of the FBD program, evaluating all blocks from left to right and top to bottom, then writes outputs at the end of the scan. The minimum cycle time depends on the number and type of blocks in the program.

For the V/F program above (one amplifier, one math instruction, one asynchronous pulse generator, one relay), the cycle time measured on a 0BA8 module is approximately 0.8-1.2 ms, which supports output frequencies up to about 400 Hz in theory. The transistor output itself does not impose a limit lower than this; the 10 Hz figure in the manual reflects the conservative rating for the most demanding load conditions.

For the design target f_max = 10 Hz the headroom is enormous. To extend f_max to 100 Hz while keeping the linear relationship, scale the math instruction by a factor of 10 (PV = 10⁵ / (AV + 1)) so that the resulting period is one-tenth of the original. The cycle time of the expanded program stays under 2 ms and the pulse train is clean.

Transfer Characteristic and Timing Diagram

The transfer characteristic from input voltage to output frequency is linear by construction of the math formula. The corresponding pulse-train waveforms at three sample voltages are shown below.

Wiring and Pin Assignment

The base module of the LOGO! 0BA8 has removable screw terminals. The pinout of the analog and digital sections relevant to this design is summarised below.

For LOGO! 6 (0BA6) base modules, the analog input I7 is labelled AI1 with the same 0-10 V range. The transistor output Q1 is wired identically. For further information consult the LOGO! 8 system manual available on the Siemens Industry Online Support portal.

Recommended external protection

• 1N4007 freewheeling diode across inductive loads, cathode to +24 V.
• 10 kΩ resistor in series with AI1 to limit fault current if the source exceeds 10 V.
• Zener diode 11 V (1N4741) across AI1+ and AI1- to clamp transients.
• Ferrite bead on the analog cable if routing near VFD output cables.

Commissioning Procedure

Commissioning follows a structured sequence so that any deviation between expected and measured frequency points to one specific subsystem.

1. Verify wiring. With the LOGO! de-energised, confirm that the analog source positive is on I7+, the analog source negative is on I7-, and that Q1 is wired to the load's low-side terminal. Apply 24 V to L+/M.
2. Configure analog input. On the LOGO! display or in Web Editor, navigate to AI1. Set the sensor type to 0-10 V. The display should show a value between 0 and 1000 as the analog input sweeps from 0 to 10 V.
3. Apply 0 V and check for stopped output. Short the AI1 input or set the source to 0 V. Q1 should remain LOW indefinitely. The math output PV will be 1,000,000 μs and the pulse generator period will be 1 s — effectively one pulse per second, which is the lowest non-zero output. Verify by disconnecting the AI1 wire entirely: the math instruction will saturate and the output will appear at the minimum frequency.
4. Apply 5 V and measure frequency. Set the analog source to 5.00 V. The expected output frequency is approximately 5.0 Hz ± 5 %. Measure with a frequency counter or by timing 10 pulses on a stopwatch (20 seconds expected). If the measured value is off by more than 10 %, check the amplifier gain and the math instruction's constant numerator.
5. Apply 10 V and measure full-scale frequency. Set the analog source to 10.00 V. The expected output frequency is 10.0 Hz ± 5 %. If the measured frequency is half of expected, the constant numerator in the math block is set to 5×10⁵ instead of 10⁶; recheck the value.
6. Linearize at three points. With V_in set to 1 V, 5 V, and 9 V, record the measured frequency. A linear regression should yield slope = 1.00 Hz/V and intercept ≈ 0 Hz within the tolerance of the analog amplifier and the math block's division rounding.
7. Verify under load. Connect a realistic load (24 V solenoid, indicator lamp, or counter input) and repeat step 5. Confirm that the load voltage waveform is clean with no ringing and that the frequency is unchanged.

Display Configuration for Local Indication

The LOGO! on-board display (LOGO! 8 with article suffix MD or the LOGO! TDE expansion display) supports up to four message lines that can be used to show the live analog value and the current pulse period. In LOGO! Soft Comfort, drag a Message Text block onto the diagram and configure it as follows:

• Line 1: V_in = [AV ÷ 100] V
• Line 2: f_out = [10⁶ ÷ PV] Hz
• Line 3: Q1 = [Q1 state]

The [AV ÷ 100] syntax is the LOGO! Soft Comfort placeholder for live analog value display. Enable bar-graph mode for an at-a-glance indication of the analog input level.

Troubleshooting Matrix

Higher-Frequency Pulse Alternatives

When the application requires f_max above the practical limit of the LOGO! transistor stage (above 100 Hz with confidence), the V/F conversion should be off-loaded to a dedicated converter IC. Two proven options exist.

External V/F converter

The Texas Instruments LM331 is a precision V/F converter that accepts 0-10 V on its input and produces a pulse train up to 100 kHz with linearity of 0.01 %. The full datasheet is published on the TI product page (LM331 datasheet). The LOGO!'s role reduces to providing the 0-10 V analog setpoint (still using the analog amplifier from this article) and reading the LM331's open-collector pulse output on a digital input that supports high-speed counting. Counter input I3-I6 on the 0BA8 base module can accept frequencies up to 5 kHz reliably without additional filtering.

PWM-output analog block

The LOGO! Soft Comfort PWM function block, available since firmware FS:04 on the 0BA8 platform, generates a fixed-frequency PWM output with variable duty cycle. While not strictly a V/F converter, a PWM signal integrated by a downstream RC network yields an analog voltage proportional to duty cycle. The reciprocal application (analog to PWM duty cycle) is supported by the Analog PWM block on the same firmware line. This is documented in the LOGO! 8 system manual on Siemens Industry Online Support.

Higher-end LOGO! variants

LOGO! 8 (0BA8) modules with the suffix S or CE add additional digital outputs and faster processors. They share the same 10 Hz transistor specification, so for frequencies above 100 Hz the LM331 route remains the recommended approach.

Frequently Asked Questions