Resolving SMH-2Gi Slave Memory Map One-Change Lag Fault

Rebuilding the affected slave memory map removes the one-change value lag without adding a write-delay workaround. The decisive test is whether the fault follows a specific map object while the controller, write logic, and target remain unchanged.

What reading identifies the failure?

Look at the trend first. Record the value entered on the controller screen, the value presented to the write function, and the value read back from the slave map for several consecutive edits. In the failing Broken project, the mapped variable Int receives the write command before its input has updated, so the transaction carries the previous value. The new input value becomes available only after that write.

This ordering produces a repeatable signature: the destination remains exactly one operator change behind. After several edits, the displayed value appears to jump because each write applies the preceding entry rather than the current one. That is different from random communications loss, scaling error, or controller scan jitter.

Does the trace show a transaction delay or bad mapping?

Make three distinct edits and compare each write payload with the current and previous screen values. If write 2 contains entry 1 and write 3 contains entry 2, the problem is an update-order fault in the signal chain. Continue by testing the memory-map object. If values are unrelated, inspect addressing, data type, scaling, and communications status before changing timing.

A delay on the write pulse can make the project operate because it gives Int time to update before the request is issued. That is a workaround, not a diagnosis. It couples correct operation to execution order and can fail again when project load, task order, or communications behavior changes. Tuning does not fix wiring, and timing does not repair a damaged mapping definition.

Do not convert a one-change lag into a guessed delay value. No required delay interval was established. If a temporary delay is unavoidable, determine it from an online trace that shows the input update and write-request edges, then retest under the slowest observed update condition.

Does the fault follow the memory map?

Place a known-working and failing slave map in the same master project, then drive both with equivalent write logic. This isolates the configuration object from the controller and program execution. The supplied master test contained two slave memory maps: one worked, while Broken remained one change behind under the same write sequence. That result points to the stored map definition or its generated internal metadata.

1. Use the same source value and equivalent change pulse for both map objects.
2. Write a short sequence of distinct integers and log the source, payload, and destination for every operation.
3. If only Broken lags, stop adjusting global controller timing and proceed to map reconstruction.
4. If both maps lag, inspect execution order between the screen variable, change detector, and write request.
5. If the fault moves with an address or target rather than the map, inspect that target's address and data definition.

The behavior was reproduced with SMLogix 3.27.0444 on an SMH-2Gi having kernel 2.6.29.696, libraries 0.1.622, Logix 0.266.3, menu 1.0.742, modem 0.1.657, Qt libraries 0.1.596, skipper 0.1.840, software 265.598, SQL 0.0.606, and TemplateLite 1.1.594. Other unspecified versions behaved similarly, so changing versions alone is not a demonstrated repair.

Does the target address affect the diagnosis?

The illustrative setup assigned the slave device the same address as the controller running the project, causing the controller to write to itself. Same-controller polling is not a supported operating mode, so use it only to expose sequencing and never as the final acceptance test.

Repeat the test with a second controller as the target. If the same map remains one edit behind, the loopback arrangement is not the cause. If the problem occurs only during self-addressing, replace the setup with the intended external topology and verify the result there. In either case, confirm that the slave address in the project matches the actual destination before interpreting the value trace.

Can a data-width mismatch reveal map damage?

Inspect the map's declared type, occupied words, and write span. A previous failure mode involved a float/real variable for which only one word was written. The remaining word retained old data, so the destination did not receive the complete real value. Deleting the slave definition and creating a new memory map corrected that behavior.

For an integer lag, verify that the source and mapped destination use the same integer representation. For a real value, verify that the complete multiword value is transferred and that source and destination agree on word order. Watch each occupied word online during a controlled write. One changing word and one stationary word identifies an incomplete transfer; both words changing does not by itself prove correctness, so compare the reconstructed destination value as well.

These checks matter because a map can look correct in the editor while its generated internal representation behaves differently. Re-entering one variable may not regenerate every dependency. When the fault stays attached to the map object, reconstruct the full slave map.

How do you rebuild and verify the resolving branch?

1. Save a backup of the project and record the existing slave address, variable names, data types, word locations, screen bindings, and logic connections.
2. Capture a failing sequence that shows the current screen entry, the mapped Int input, the write pulse, and destination readback. This becomes the acceptance baseline.
3. Delete only the affected slave memory-map definition. Do not delete unrelated working maps.
4. Create a new slave definition and reproduce the recorded address, variables, types, and locations. Reconnect every screen and logic reference to the new variables.
5. Compile and download the rebuilt project using the normal project workflow.
6. Enter at least three distinct integer values. For every edit, confirm that the write payload equals the current entry rather than the previous one.
7. Test all rebuilt multiword variables and observe every occupied word. Confirm the destination reconstructs the intended value.
8. Remove the temporary write delay and repeat the test. The repair passes only when current values transfer correctly without timing compensation.
9. Perform the final test with the intended external target and address arrangement, not only the self-addressed demonstration.

For large projects, compare every recorded map entry and connection after reconstruction. Missing bindings can imitate a communications fault, while a displaced word can corrupt adjacent values. Retain the original project backup until every mapped item has passed a read/write test.

FAQ