S7-1200 LAD Boolean Sequencer: Variable Phase Times in TIA Portal

Overview

The pattern of cycling three Boolean outputs so that exactly one output is TRUE at any instant, with each output held for an independently-configurable duration, is a recurring requirement on test rigs, lighting sequencers, conveyor indexes, and actuator validators. On the SIMATIC S7-1200 family programmed with Ladder (LAD) in TIA Portal, the cleanest realization is a reusable Function Block (FB) that accepts three TIME durations T1, T2, T3 and drives three Boolean outputs Q1, Q2, Q3 in a strict one-hot sequence. The block runs cyclically inside OB1 (or any cyclic OB), uses IEC 61131-3 TON timers to enforce each phase, and never terminates; the loop is closed by feeding phase 3 back to phase 1.

This reference covers the design of a three-phase sequencer on the S7-1200 (CPU 1211C / 1212C / 1214C / 1215C / 1217C) using TIA Portal V16 through V19. It includes a pure-LAD implementation built on multi-instance TON blocks, an SCL alternative for comparison, the timing math that makes the one-hot pattern exact, and a commissioning/verification checklist for catching the typical OB1 cycle and race conditions encountered on real hardware.

Prerequisites

Before designing the sequencer, confirm the following on the engineering station and the target PLC:

• Engineering software: TIA Portal V16, V17, V18, or V19 with the SIMATIC S7-1200 hardware support package installed. TIA V15.1 also supports the S7-1200 family but limits a few instruction variants.
• Target CPU: Any S7-1200 (1211C, 1212C, 1214C, 1215C, 1217C) with firmware 4.2 or higher. The installed firmware can be read online via Online > Accessible nodes in TIA Portal.
• Firmware knowledge base: Siemens maintains the S7-1200 firmware release notes collection in Siemens Industry Online Support. Search the entry titled "SIMATIC S7-1200 CPUs - Firmware updates" for the changelog relevant to your service pack.
• Memory: A multi-instance DB is generated automatically by TIA when the FB is called with its own data block. For a three-phase sequencer with three single-instance IEC timers, plan on roughly 80 to 120 bytes of work memory plus the instance DB overhead.
• OB1 cycle budget: The S7-1200 OB1 cycle time must be at least one order of magnitude shorter than the shortest phase. A 1 ms OB1 is feasible on CPU 1214C / 1215C and is recommended when T1, T2, or T3 drops below 20 ms.

S7-1200 Timer Fundamentals (IEC 61131-3)

The S7-1200 instruction set implements the four IEC-standard timer function blocks: TON, TOF, TP, and TONR. For a one-hot Boolean sequencer, only TON (and occasionally TP) is required.

The PT (preset time) input accepts a TIME literal. S7-1200 supports both literal notation T#2s500ms and a TIME tag of DWord (32-bit) width. Time resolution is 1 ms internally; the value is a signed DWord in milliseconds with the layout defined in the SIMATIC S7-1200 Programmable Controller System Manual, available from Siemens Industry Online Support.

Implementation Architecture

The cleanest design is a single FB with three parallel TON timers that drive the three outputs, plus a state-machine network that arms exactly one timer at a time. The FB interface:

Multi-instance timers keep the FB self-contained: a single instance DB is generated for the entire block and holds TonPhase1, TonPhase2, TonPhase3 as nested IEC_TIMER structures of 16 bytes each.

Step-by-Step: Building the Sequencer FB in LAD

Create the project structure first, then build the FB network-by-network.

Step 1 – Create the FB

1. In the project tree, expand Program blocks > Add new block > Function Block.
2. Set Name = FB_Sequencer3, Language = LAD. Enable Add new instance DB automatically in TIA V17 and later, or create DB_Sequencer manually in older versions.
3. Open the FB and declare the interface as shown in the table above.

Step 2 – Network 1: Cold-start / Reset

Drive State := 0 on first scan or when the Reset input pulses. In LAD, this is a set-dominant flip-flop built from a SR block:

     FirstScan    Reset
     ---||---------|(S)
                        ]---[SR]---( State := 0 )
     ReverseQ     --|(R)

Equivalent in LAD: drag an SR (Set/Reset flip-flop) onto the network. Wire the set input to (FirstScan OR Reset) and the reset input to the inverse of Enable AND NOT StateDone. This guarantees a deterministic phase 1 on every CPU cold start.

Step 3 – Networks 2/3/4: Parallel TON timers

Each phase has its own TON with PT bound to the corresponding duration tag:

Network 2:
     State = 0
     ---||--------[TON "DB_Sequencer".TonPhase1, PT := #T1]---( )
     Phase1Active --( )

Network 3:
     State = 1
     ---||--------[TON "DB_Sequencer".TonPhase2, PT := #T2]---( )
     Phase2Active --( )

Network 4:
     State = 2
     ---||--------[TON "DB_Sequencer".TonPhase3, PT := #T3]---( )
     Phase3Active --( )

To create the multi-instance timer in LAD, drag Timers > TON onto the rung, then click the timer instance selector and pick Multi-instance > TonPhase1 from the FB static section. TIA Portal automatically generates the IEC_TIMER declaration.

Step 4 – Network 5: Output decoder (one-hot)

Decode State into Q1, Q2, Q3 with mutually exclusive comparators. This guarantees the one-hot invariant Q1 XOR Q2 XOR Q3 = TRUE at all times when Enable is TRUE.

     "State"      "Enable"
     ---[==0]--------||--------( Q1 )
     "State"      "Enable"
     ---[==1]--------||--------( Q2 )
     "State"      "Enable"
     ---[==2]--------||--------( Q3 )

Step 5 – Network 6: Phase advance logic

On the rising edge of each TON's Q output, advance State and reset the completed TON:

Network 6a (advance 0 -> 1):
     "DB_Sequencer".TonPhase1.Q   State=0
     ---||( R_TRIG )----------||--------[INC "State"]
                                            ]
     "DB_Sequencer".TonPhase1   ---( R )

Network 6b (advance 1 -> 2): same pattern with TonPhase2 and State=1
Network 6c (advance 2 -> 0): same pattern with TonPhase3 and State=2

An R_TRIG (rising-edge detector) on the TON.Q signal prevents a single OB1 scan from advancing State more than once when the timer remains latched.

Step 6 – Call the FB in OB1

Drag the FB onto an OB1 rung. TIA Portal prompts for an instance DB; select Single Instance and name it DB_Sequencer. Bind the inputs:

CALL "FB_Sequencer3", "DB_Sequencer"
  Enable := "Run_Sequencer"
  T1     := T#2s
  T2     := T#500ms
  T3     := T#1s500ms
  Reset  := "Seq_Reset"
  Q1     := "Seq_Q1"
  Q2     := "Seq_Q2"
  Q3     := "Seq_Q3"

Alternative: SCL Implementation

For comparison, the same sequencer fits in roughly twenty lines of SCL inside an FB. The SCL form makes the state machine explicit and is often easier to maintain than the equivalent LAD networks.

FUNCTION_BLOCK "FB_Sequencer3"
VAR_INPUT
    Enable : BOOL;
    T1, T2, T3 : TIME;
    Reset : BOOL;
END_VAR
VAR_OUTPUT
    Q1, Q2, Q3 : BOOL;
END_VAR
VAR
    State : INT;
    TonPhase1 : IEC_TIMER;
    TonPhase2 : IEC_TIMER;
    TonPhase3 : IEC_TIMER;
END_VAR
BEGIN
    IF Reset THEN
        State := 0;
    ELSIF Enable THEN
        CASE State OF
            0:
                TonPhase1(IN := TRUE,  PT := T1);
                TonPhase2(IN := FALSE, PT := T2);
                IF TonPhase1.Q THEN
                    TonPhase1(IN := FALSE, PT := T1);
                    State := 1;
                END_IF;
            1:
                TonPhase2(IN := TRUE,  PT := T2);
                TonPhase3(IN := FALSE, PT := T3);
                IF TonPhase2.Q THEN
                    TonPhase2(IN := FALSE, PT := T2);
                    State := 2;
                END_IF;
            2:
                TonPhase3(IN := TRUE,  PT := T3);
                TonPhase1(IN := FALSE, PT := T1);
                IF TonPhase3.Q THEN
                    TonPhase3(IN := FALSE, PT := T3);
                    State := 0;
                END_IF;
        END_CASE;
    END_IF;

    Q1 := (State = 0) AND Enable;
    Q2 := (State = 1) AND Enable;
    Q3 := (State = 2) AND Enable;
END_FUNCTION_BLOCK

The SCL version relies on the IEC_TIMER data type and explicit IN/PT refresh, which matches the behavior of the TON box in LAD. Mixing the two languages inside the same project is allowed by TIA Portal; the FB can be written in LAD while the calling code lives in SCL.

Timing Accuracy and OB1 Cycle Considerations

The achievable timing accuracy of the sequencer is dominated by three contributors: the OB1 cycle time of the CPU, the resolution of the TIME type, and the propagation of the timer state through the cyclic scan.

The S7-1200 TIME type is a signed 32-bit integer with 1 ms resolution covering approximately ±24 d 20 h 31 m 23 s 648 ms. For typical PT values (10 ms – 60 s) this range is irrelevant. The OB1 cycle time on a CPU 1214C DC/DC/DC with firmware 4.4 in default configuration is approximately 1–2 ms for a sequencer block this small. Each pass through the sequencer evaluates three TON instances and a state comparator, contributing well under 100 µs of scan time. The bottleneck is therefore not the sequencer itself but the broader OB1 program.

For deterministic time measurement, configure a hardware interrupt OB (OB40) tied to a high-frequency counter pulse and route the sequencer start to that OB. For most test-rig applications, however, the standard cyclic OB1 is sufficient and the jitter is bounded by the OB1 period plus the IEC timer's 1 ms update granularity.

Calculating the cycle budget

The fundamental inequality for any one-hot sequencer is:

T_OB1 << min(T1, T2, T3)

A practical rule is to keep the OB1 period below 10 % of the shortest phase. If T1 = 50 ms, T_OB1 should be 5 ms or less. The S7-1200 diagnostic buffer lists the longest, shortest, and current OB1 cycle under Online > Diagnostics > Cycle Time.

Verification Procedure

After downloading the project to the CPU, validate the sequencer against the following checks. Each step assumes the online connection is established and the sequencer instance DB is in RUN.

1. Static inspection: Open DB_Sequencer in online mode and confirm the initial values of State, TonPhase1.IN, and the output tags. Expect State = 0, Q1 = TRUE, Q2 = FALSE, Q3 = FALSE after a CPU STOP→RUN transition.
2. Watch table: Create a watch table containing DB_Sequencer.State, DB_Sequencer.Q1, DB_Sequencer.Q2, DB_Sequencer.Q3, and the elapsed time DB_Sequencer.TonPhase1.ET. Force Enable = TRUE and observe State advancing through 0 → 1 → 2 → 0.
3. Trace recording: Use Traces > Configuration to record Q1, Q2, Q3 at a 1 ms sampling rate. Verify that the high time of each output equals T1, T2, T3 within ±1 OB1 cycle.
4. Online trend: Right-click any tag in the watch table and select Trend View for a quick visual check of the one-hot pattern.
5. Diagnostic buffer: After a 60 s run, open Online > Diagnostics > Diagnostic Buffer and confirm no events with timestamp overlapping the run window.
6. Logic analyzer cross-check: For critical timing, mirror Q1, Q2, Q3 to a free digital output and capture with an external logic analyzer or oscilloscope. The S7-1200 digital output transition time is in the low microseconds, well below T_OB1.

If any output remains TRUE for longer than its configured time, the typical root cause is a missing reset coil on the preceding TON. If State jumps by two values at once, two TON.Q signals latched simultaneously; add an intermediate reset between phase transitions.

Troubleshooting Matrix

Advanced Extensions

Once the three-phase core is stable, several extensions are common in field deployments. Each is a small change to the FB rather than a redesign:

• Variable phase count: Replace the fixed State : INT range with a modulo counter and an array of IEC_TIMER instances. The maximum phase count is bounded by the work-memory budget (one IEC_TIMER ≈ 16 bytes).
• External trigger: Add a BOOL input that pauses the sequencer mid-phase without losing the elapsed count, by gating Enable rather than resetting TON.
• HMI integration: Bind T1, T2, T3 to WinCC Comfort/Advanced input fields and add a trend view of Q1, Q2, Q3 for verification.
• Profinet/Modbus exposure: Tag the outputs on the S7-1200 with a DB that is also reachable from a Profinet device or a Modbus TCP server block, allowing remote test rigs to observe the pattern.
• Edge-aligned reset: Combine Reset with an R_TRIG so the sequencer restarts on the rising edge only, eliminating bounce-induced double resets.

Notes on Ladder Idioms

Two LAD-specific idioms recur when converting a TIMER-based sequencer to the graphical editor:

1. Direct tag on PT: drag a tag from the project tree onto the PT input of a TON box; TIA Portal preserves the binding across recompiles and downloads.
2. Reset coil vs. IN assignment: a reset coil on a TON's instance tag clears both IN and the elapsed-time counter. Use this only when the next phase must start from zero elapsed time; for a pure refresh without resetting elapsed, drive IN := FALSE explicitly via the SCL form or a separate contact.
3. Comparator blocks: the LAD EQ_I / EQ_DInt blocks are the canonical way to evaluate State = 0/1/2. Place them on a single rung with parallel contacts and parallel output coils for the decoder network.

FAQ