Sizing DOC for 11/0.433 kV 1 MVA Parallel Transformer Protection

System Overview and One-Line Topology

The installation comprises a 3-panel 11 kV vacuum circuit breaker (VCB) switchboard (one incomer, two outgoing feeders) with Siemens 7SJ6015 numerical overcurrent relays on each panel. Each outgoing feeder supplies one 11/0.433 kV, 1 MVA ONAN distribution transformer (Dyn11 vector group, off-circuit tap-changer). The two transformers operate in parallel on the LV side via a normally-closed ACB bus-coupler fitted with an LSIG solid-state release; the LV switchboard itself has two incomer ACBs plus the bus-coupler, all LSIG. The LV outgoing feeders, of which the largest is a 630 A frame, carry no dedicated earth-fault element.

Operating two 1 MVA units in parallel on a closed LV bus-coupler presents a 2 MVA equivalent source for every downstream fault. This drives the protection-engineering decisions that follow:

1. Any single trip that opens the HV breaker — whether initiated by the 7SJ6015, by upstream protection, by a transformer fault, or by an LV bus fault that escalates to a breaker trip — drops both transformers. The two units share a common 11 kV bus section and a common LV bus section. The parallel arrangement is therefore not redundant unless the bus-coupler is operated normally open with feeders segregable.
2. A bus-section fault is fed from both transformers simultaneously, so the bus-coupler isolates one bus section from the other rather than from upstream. The bus-coupler cannot by itself clear a fault at its LV terminals.

The three protection questions to settle are therefore:

• Does the scheme need directional overcurrent (ANSI 67) or directional earth fault (ANSI 67N)?
• If yes, where do the CT and VT sit — on the HV side, LV side, or both?
• Is transformer differential (ANSI 87) or REF (ANSI 87N / 64R) the more appropriate primary protection for the unit?

Transformer and Switchboard Ratings

Before any pickup value is set, fix the system operating currents. For the 1 MVA 11/0.433 kV three-phase unit:

HV full-load current (line-to-line 11 kV):

I_FL,HV = S / (sqrt(3) × V_LL) = 1,000 kVA / (1.732 × 11 kV) ≈ 52.5 A

LV full-load current (line-to-line 0.433 kV):

I_FL,LV = S / (sqrt(3) × V_LL) = 1,000 kVA / (1.732 × 0.433 kV) ≈ 1,333 A

Combined LV current with both transformers running and the bus-coupler closed:

I_LV,comb = 2 × 1,333 A ≈ 2,666 A

The LV ACB incomer and bus-coupler frames must be sized for at least 1,600 A nominal; typical installations use ACB frames 1,600 AF with adjustable plug ratings 1,000–1,600 A. Verify the ACB i²t let-through against the kA available at the LV bus and the conditional short-circuit rating I_cc of the assembly.

Short-Circuit Current Calculations (IEC 60909)

Use IEC 60909 for the maximum short-circuit duty at the LV bus. With two transformers in parallel through the bus-coupler, the parallel impedance Z_k,parallel is Z_k,single / 2.

Single-transformer LV-side initial symmetrical short-circuit current at 0.433 kV:

I"_k (single) = I_FL,LV / Z_k(pu) = 1,333 A / 0.0625 ≈ 21.3 kA

Parallel-transformer LV-side initial symmetrical short-circuit current (worst case with bus-coupler closed and stiff source):

I"_k (parallel) = 2,666 A / 0.03125 ≈ 85.3 kA peak

For an LV bus-section fault with the bus-coupler open, only one transformer contributes, so the single-transformer figure (≈21 kA) is the design level for grading the LV L-stage against the LV outgoing. The parallel figure (≈85 kA) is the design level for the ACB breaking capacity and for the bus-coupler I_cm peak let-through.

Through-fault current at the HV side for an LV three-phase bolted fault (per transformer, single contribution):

I"_k,HV (single xfmr) = 21,300 A × (0.433 / 11) ≈ 839 A on HV

For parallel contribution, scale by 2:

I"_k,HV (parallel) ≈ 1,678 A on HV

The 839 A figure is what the 7SJ6015 sees during an LV bus-section fault, and is the value used to set the 50 (instantaneous) and to check the through-fault stability of any differential added later.

ANSI/IEEE Device-Number Map

The protection functions installed or recommended for this scheme map to the standard ANSI C37.2 device numbers, identical to IEC 60255 device numbering where applicable:

Do You Need Directional Overcurrent? Decision Matrix

Directional OC (ANSI 67) is required only when the same CT may carry current in both directions during normal operation. In a simple radial feeder, it adds nothing; in a network where the breaker can see source-side or load-side fault current, it discriminates the trip.

For the present single-incomer 11 kV switchboard with a closed LV bus-coupler, directional OC is not strictly required. The HV 7SJ6015 will see forward current for every LV fault regardless of which transformer feeds it. The protection coordinator's priority here is grading of the IDMT time-current curves, not directionality. Reserve 67 / 67N for ring or second-source schemes.

DOC Placement: HV Side or LV Side?

If directional OC is added (for ring operation, second source, or for incremental reliability on paralleled transformers), the practical question is where to put the directional element.

HV side (one directional element per 11 kV outgoing):

• Single CT location per feeder; minimum hardware.
• VT requirement: a feeder-side VT or voltage-sensing module must be added on each outgoing panel.
• Polarisation source (the reference phasor for direction) is the bus-side voltage at 11 kV, robust against upstream source-swinging.
• Forward direction by convention = current flowing from 11 kV bus into the transformer (i.e., feeder fault).

LV side (one directional element per LV ACB incomer):

• CT already exists inside the ACB; effectively free.
• VT requirement: a phase-to-phase VT or three single-pole VTs at the LV terminals of each ACB; add to the ACB panel as a retrofit.
• Polarisation is local, so sensitivity at low fault-current levels is improved.
• Each ACB can clear its own contribution independently from the bus-coupler.

For a retrofit where shutdown time matters, the LV-side placement is usually preferred because:

1. The ACB-compartment CTs are already in place; no HV outage required.
2. An LV VT module can be added to the ACB panel without taking the 11 kV bus out.
3. The polarisation quantity mirrors across both LV incomers and the bus-coupler, simplifying the grading matrix.

Differential (87), REF (87N / 64R), and Partial Differential (87B) Alternatives

Directional OC improves grading; differential (87) and REF catch the fault classes that grading cannot cover:

• Winding-to-winding short circuits inside the transformer tank
• Inter-turn faults not visible at the terminals
• Low-level LV earth faults restricted to the LV winding
• Tap-changer internal faults

ANSI 87 (current differential) requires CTs on both HV and LV terminals of the transformer. The 7SJ6015 does not provide a 87 element; a separate numerical relay (Siemens 7UT63 / 7UT64 series from the Siemens Industry Online Support portal, or equivalent from another vendor) must be installed with matched-ratio HV and LV CTs. Retrofitting HV-side CTs at the transformer terminals requires a primary-side outage; for a 1 MVA unit installed in 1959, this is rarely justifiable on its own — it is justified as a single protection upgrade covering both transformers.

ANSI 87N / 64R (Restricted Earth Fault) is a low-cost alternative for grounded-wye LV windings (Dyn11 satisfies this). It needs only:

• A neutral CT on the LV star point of the transformer
• The existing LV ACB phase CTs connected residually
• A high-impedance or biased differential module (often implemented inside the 7SJ60-series relay via a software function, or separately as a REF module)

REF detects single-phase-to-ground faults on the LV winding up to the LV terminals, with sensitivity down to about 10 % of CT rating. It does not detect HV-side internal faults. For a 1959-vintage installation where the LV neutral CT may already be in place for ground-fault detection, REF is the most cost-effective protection upgrade. The 7SJ6015 firmware does not include REF directly; pair it with a separate neutral-voltage / neutral-current detection scheme, or replace the 7SJ6015 with a 7UT6 series on each transformer.

Partial differential (ANSI 87B) uses two sets of CTs on the LV side only — one near the transformer LV terminal and one inside the ACB. It protects the LV cable between the transformer and the ACB but not the transformer itself. Useful where the only concern is cable damage for a long LV run.

Coordination Sequence and Grading Intervals

Typical grading for the present scheme with bus-coupler closed, single 11 kV incomer:

The grading interval between IDMT curves on adjacent stages is typically 0.30–0.40 s at the maximum through-fault current, including CT tolerances of 5 % and relay timing tolerance of 5 % per IEC 60255-151. At the parallel through-fault current the HV stage sees roughly 1,678 A flowing through the 7SJ6015. With a pickup at 52.5 A and a Standard Inverse curve, the operating time at 1,678 A is approximately:

t_op = 0.14 × TMS / ( (I/I_p)^0.02 − 1 ) — confirm with the project's grading-study tool rather than the simplified form above.

CT, VT, and Wiring Requirements

HV-side CT (mounted inside the 11 kV VCB panel, supporting the 7SJ6015):

• Primary current ≈ 52.5 A; standard ratio 100/5 or 75/5.
• Class 5P10 minimum; for directional applications, 5P20 at the polarising current.
• Verify knee-point voltage V_k ≥ 2 × I_sc × (R_burden + R_lead) to avoid saturation during the close-in heavy fault.
• CT polarity: P1 toward the 11 kV bus (away from the transformer), per the relay wiring diagram.

LV-side CT (inside the ACB):

• Standard frame ratios 1,600/1 or 2,000/1 supplied by the ACB manufacturer.
• For REF, a neutral CT on the LV star point of each transformer, ratio 100/1 or 200/1 typically.
• For DOC, an Earth-Fault CT or core-balance CT may already be fitted inside the ACB for residual earth-fault detection.

Voltage transformer for the directional element:

• 11 kV side: 11/√3 : 0.11/√3 kV, class 3P, secondary 100/√3 V, fused secondary.
• LV side: 0.433/√3 : 0.11/√3 kV, class 3P, fused secondary with automatic short-circuit protection.
• Polarisation phase-angle calibration: phase A voltage in phase with phase A current under a known direction of power flow. Confirm with the load-current check described in the commissioning section.

Secondary wiring:

• 2.5 mm² copper minimum for CT secondary; 1.5 mm² for VT secondary.
• Screened cable for VT secondary, earthed at the relay panel end only to avoid circulating currents.
• CT secondary windings earthed at one point only (at the relay panel earth bar).
• Phase rotation must be U-V-W on the primary matching u-v-w on the secondary winding; mismatch is one of the most common causes of directional-element mis-operation after a retrofit.

Siemens 7SJ6015 Family — Setting Parameters

The 7SJ60 is a numerical overcurrent relay with phase and earth-fault elements, inrush restraint, and optional directional capability on the 7SJ61 / 7SJ62 variants. The 7SJ6015 designation indicates a specific ordered variant within the family; settings are entered in primary amperes via DIGSI 4 or the front-panel keypad. The address numbers below are typical for firmware V4.2 or later; refer to the device-specific operating manual from the Siemens Industry Online Support portal for the exact menu layout and the exact parameter convention for 67/67N where the directional element is enabled.

Address      Setting                          Value
3001         I> Pickup (51)                   52.5 A   (1.0 × FLA)
3002         I> Characteristic curve          Standard Inverse (SI)
3003         I> TMS (Time Multiplier)         0.40
3004         I>> Pickup (50)                  525 A    (10 × FLA)
3005         I>> Definite-time delay          0.08 s
3011         I0> Pickup (51N)                 0.10 × FLA = 5.3 A
3012         I0> Characteristic               Standard Inverse
3013         I0> TMS                          0.30
3014         I0>> Pickup (50N)                2 × FLA = 105 A
3015         I0>> Definite-time delay         0.10 s
3101         Inrush Restraint                  ON
3102         Cross-block                       OFF
3201         67 Directional OC                 OFF (unless ring / second-source)
3202         67N Directional EF                OFF (unless ring / second-source)
3301         REF / 87N enable                  ON (recommended)
3302         REF operate value                  0.10 × CT sec

Inrush, DC Offset, and CT Saturation

Transformer energising inrush can reach 6–8 × FLA for 100 ms to several seconds, depending on residual flux. The 7SJ6015 default 2nd-harmonic restraint detects a 2nd-harmonic component above approximately 15 % and blocks the 50 and 51 elements for the duration of the inrush. Enable and verify before commissioning — an absent or disabled inrush-restraint logic generates nuisance trips on every energisation.

Through-fault DC offset (per IEC 60909): peak fault current i_p = κ × √2 × I"_k where κ = 1.02 + e^{(−π / (X/R))}. For X/R = 8 (typical 1 MVA transformer), κ ≈ 1.76, so i_p ≈ 1.76 × √2 × 21,300 ≈ 53 kA peak at LV bus (single transformer). Verify the ACB I_cm (peak making capacity) ≥ 53 kA peak.

CT saturation at heavy fault: ensure the CT kneepoint V_k satisfies:

V_k ≥ 2 × I_sc(ct sat) × (R_ct + R_lead + R_relay)

where R_ct is the CT secondary winding resistance, R_lead is the loop lead resistance (typically 0.5–1.0 Ω for a 50 m cable run with 2.5 mm² copper), and R_relay is the relay input impedance (typically <0.1 Ω for electromechanical, 0.01 Ω for numerical input). For an LV ACB CT inside the breaker, R_lead is negligible and the manufacturer specifications apply.

Commissioning and Verification

After settings are loaded but before energising, perform the following checks:

1. CT & VT polarity and phase-rotation check: at 1 × FLA load current, confirm the relay measures line voltage leading the corresponding phase current by the system impedance angle (typically 60–75° for industrial networks).
2. Secondary injection at 0.5, 1.0, 5.0, and 10 × pickup to verify pickup threshold and timing against IEC 60255-151 tolerance bands (±7.5 % current, ±5 % timing).
3. Directional logic test: inject forward current at angle −60° from the polarisation voltage; confirm the directional flag picks up. Reverse the phase-rotation or apply +120°; confirm no pickup.
4. REF logic test: inject residual current through the LV phase CT summation; confirm pickup at the set residual value.
5. Trip matrix test: simulate a three-phase LV bus fault via primary or secondary injection; confirm the LV ACB L-stage trips first, then the bus-coupler, then the HV 51, then the HV 50, then the 11 kV incomer.
6. End-to-end trip: pulse the trip output of each relay; confirm the associated breaker opens within the design clearing time (typically ≤ 100 ms for the HV 50 element).
7. Inrush-restraint test: force a transformer energisation (no-load closure); confirm the 7SJ6015 does not issue a trip during inrush decay.
8. VT fuse-fail (VTS) test: blow the VT secondary fuse; confirm the directional element blocks trip and the relay generates an alarm.

Operating-Sequence Validation and Documentation

For the present scheme, validate the operating sequence with a written coordination study and an on-site trip matrix. Document the coordination and update the single-line diagram to reflect the final settings.

Fault point        | ACB-A  | ACB-B  | BC    | HV-O/G 51 | HV-INC 51
-------------------|--------|--------|-------|-----------|----------
LV feeder F1       |  TRIP  |   -    |   -   |    -      |    -
LV feeder F2       |   -    |  TRIP  |   -   |    -      |    -
LV bus-section A   |  TRIP  |   -    | TRIP  |    -      |    -
LV bus-section B   |   -    |  TRIP  | TRIP  |    -      |    -
T1 internal        |  TRIP  |   -    | TRIP  |   TRIP    |    -
T2 internal        |   -    |  TRIP  | TRIP  |   TRIP    |    -
HV 11 kV bus       |   -    |   -    |   -   |   TRIP    |   TRIP
LV winding EF      |  TRIP  |   -    |   -   |    -      |    - (via 87N)
LV cable F-J       |  TRIP  |   -    |   -   |    -      |    -

If the bus-coupler and the affected LV incoming are set to identical LSI characteristics, both will trip simultaneously on a bus fault. Eliminate the race by:

• Staggering the L-stage TMS by 0.05 s between the bus-coupler and the affected incomer; the bus-coupler takes the faster (lower TMS) timer since it serves no other load once open.
• Adding a directional element to each incomer to revoke the close-on-fault contribution from the parallel transformer in the back-up logic.
• Implementing a logic interlock in the 7SJ6015 that supervises the ACB trip on the bus-coupler position (block HV 51 trip if the fault current includes contribution from the parallel side and that side's ACB has opened first).

Settings documentation requirements

A complete settings book for this scheme should record, as a minimum:

• Full-load current at every CT location.
• CT ratio, class, knee-point voltage, and burden.
• VT ratio, secondary voltage, accuracy class.
• Pickup values for every 50, 51, 50N, 51N, and 67 / 67N function.
• Curve type (SI, VI, EI, LTI, STI) for every IDMT element.
• TMS / time-multiplier setting for every IDMT element.
• Definite-time delays.
• Cross-blocks, inrush-restraint, and VTS logic states.
• Breaker-failure (50BF) initiate and timer settings if enabled.
• Logic interlock matrix where the relay participates in breaker failure or bus-section switching.

Frequently Asked Questions