TIA Portal V15.1 Clock Pulse Not Working: Troubleshooting Guide

1. Overview: Clock Memory in Siemens S7-1200 / S7-1500

Siemens S7-1200 and S7-1500 CPUs expose a set of periodic clock bits that the firmware toggles automatically at fixed frequencies. In TIA Portal these are grouped under the term Clock memory (German: Taktmerker) and are typically assigned to a single Merker byte (MB). Each bit within that byte runs at a different period:

Clock memory is part of the system memory configuration and is enabled per-CPU. The bits are read-only from the user program perspective; the firmware owns them and toggles them at the OB1 cycle start. According to the official Siemens S7-1200 G2 manual collection, the CPU properties expose two separate enable fields:

• System memory bytes – reserved bits such as the always-on bit, first-cycle bit, and diagnostic bits.
• Clock memory byte – the byte that drives the periodic pulse train.

Both features must be enabled and the configuration must be downloaded into the CPU before the bits become active. Just toggling the checkbox in the project tree without performing a hardware download to the target is one of the most common reasons the bits appear correctly in the editor but never pulse in Online & diagnostics.

2. Prerequisites

Before configuring clock memory in TIA Portal V15.1, confirm the following:

• TIA Portal V15.1 or later installed with the appropriate S7-1200 / S7-1500 device support package.
• A valid project with the target CPU added under Devices & networks.
• Online connection to the PLC (Ethernet, PROFIBUS, or PROFNET) with the CPU in STOP or RUN-P for the download.
• PG/PC interface assigned correctly (e.g. S7ONLINE → TCP/IP → Intel NIC).
• Firmware version compatible with V15.1 hardware support (S7-1200 firmware ≥ 4.2 is recommended for full V15.1 compatibility).

3. Enabling Clock Memory: Step-by-Step

1. In the project tree, expand Devices & networks and double-click the CPU icon (e.g. S7-1200 CPU 1214C DC/DC/DC, order number 6ES7214-1AG40-0XB0).
2. In the device view, switch to the Properties inspector (right pane).
3. Navigate to System and clock memory (German: System- und Taktmerker).
4. Tick Enable the use of clock memory byte.
5. Enter the byte address. Default suggestion is MB0, but for projects with existing user code, MB100, MB200, or MB255 are common choices. Avoid byte 0 if STEP 7 classic migration or any external HMI tag uses M0.0 – M0.7.
6. Optionally tick Enable the use of system memory byte and pick a different byte so that the system bits and the clock bits cannot overlap.
7. Compile the hardware configuration (Project tree → right-click CPU → Compile → Hardware (rebuild all)).
8. Download to the target (right-click CPU → Download to device → Hardware and software). Accept the prompt to overwrite the CPU configuration.
9. Switch the CPU to RUN if the download placed it in STOP.

4. Root Cause: Why the Pulse Does Not Appear

The most frequent failure mode for "clock pulse not flashing" in TIA Portal V15.1 falls into one of four root-cause families. The MB100 conflict case documented in the source thread is the textbook example of the address collision family.

4.1 Hardware configuration not downloaded

Clock memory is created in the project offline but the CPU firmware still has the prior configuration where the byte is disabled. The TIA Portal editor can resolve the symbol "Clock_1Hz" to %M100.3 in offline view, which makes it look correctly wired. In online monitoring the bit never changes state because the firmware never toggles it.

4.2 Address collision (the MB100 case)

Merker bytes are shared global memory. If any FB, FC, OB, or HMI tag table writes to MB100 — even a single bit — the firmware clock toggle and the user program write race against each other every scan. The visible symptom is that the bit appears either constantly FALSE, constantly TRUE, or jittering irregularly. The source thread confirmed this: MB100 was selected at random, the user program elsewhere touched the byte, and switching to MB200 eliminated the conflict immediately.

4.3 Optimized vs. standard block access

When clock memory is assigned inside an optimized data block region or referenced through an in/out parameter with non-optimized block access, the compiler can emit a symbolic access that the online monitor shows as correct but the firmware never updates. This is rare for Merker bits but can occur if the user accidentally defines the clock byte inside an FB's static area.

4.4 Retentive / non-retentive interaction

S7-1200 retains Merker bits across power-cycle only if the byte is flagged retentive. Clock memory bits should remain non-retentive; do not place the clock byte inside the retentive Merker range. Some users report first-scan behavior anomalies when the clock byte overlaps a retentive region because the retain initialization overrides the toggle on warm restart.

5. Solution Procedure

1. Verify online CPU properties. Go online with the CPU (Online → Go online), open Online & diagnostics → Diagnostics status and confirm the firmware version. Then open the device view and inspect the System and clock memory tab. The enabled byte must match the project setting.
2. Force a clean download. Stop the CPU (Online → Stop CPU), right-click CPU → Download to device → Hardware and software (replace all). The "replace all" option is mandatory because partial download will not refresh clock-memory enable bits on older firmware.
3. Pick a non-conflicting byte. Use the Cross-reference tool (select MB100 in any block → right-click → Cross-references or press F11) to locate every read and write site. If more than the implicit clock toggles access the byte, change the clock memory byte to a free address. MB200, MB210, MB220, MB240 and MB255 are conventional safe choices because they rarely overlap vendor library ranges.
4. Use symbolic naming instead of raw addresses. In the PLC tags table, create a tag such as Clock_1Hz of type Bool and assign its address to the chosen bit (e.g. %M200.3). Reference the symbolic name throughout the program. The benefit is twofold: the cross-reference viewer groups all uses by symbol, and any future reallocation only requires editing the PLC tag, not the program logic.
5. Compile, download, monitor. Compile the project (Project tree → Compile all), download, switch to RUN, then open a watch table or the ladder editor in online mode. The bit should now toggle at the configured period.

6. Address Allocation Best Practices

The discussion thread reinforces a discipline that experienced Siemens engineers adopt from the very first project: do not let the user choose addresses manually. The recommended workflow is:

• During initial hardware configuration, enable both system memory and clock memory at the CPU level so that TIA Portal reserves the necessary Merker bytes.
• When creating a new tag, start with a meaningful tag name, not an address. Use PLC tags → Add new and define the name, data type, and scope (global vs. local) first.
• Assign the address as the final step (right-click the tag → Define tag or Set address). TIA Portal will find the first available continuous memory on an even word boundary for word / dword data types, or the first available bool bit. This keeps user Merker usage out of the system-reserved regions.
• Treat the Merker area as three logical bands: system memory (default byte, e.g. MB0), clock memory (the configured byte, e.g. MB200), and user globals (everything else, starting from the highest byte and working downward).

7. Using Cross-References to Diagnose Conflicts

Cross-references (F11) is the canonical Siemens tool for finding every read and write site of a memory address. To use it for clock-memory debugging:

1. Right-click the suspected byte (e.g. MB100) in any block or PLC tag.
2. Select Cross-references from the context menu.
3. The lower pane lists every usage: read access (R), write access (W), in/out parameter (I/O), compared access (C), and CPU body (B).
4. If more than the implicit B entry appears, the byte is in use and must be reassigned.

For projects imported from STEP 7 classic, also check Imported S7 tags and HMI tag tables — HMI areas project as Merker accesses and frequently overlap clock memory without the developer noticing until the bit refuses to blink.

8. Verification Checklist

9. Troubleshooting Matrix

10. Alternative Pulse Generation Methods

If clock memory cannot be enabled (e.g. firmware-limited CPU or conflict with vendor library), the same periodic patterns can be generated by user code:

• IEC timer in OB1. A self-resetting TON with PT = T#1s delivers a 0.5 Hz / 50% pulse on its Q output. Cascade different PT values for 0.1 Hz, 0.2 Hz, … 20 Hz.
• Hardware interrupt OB. For sub-100 ms pulses, configure a hardware interrupt from a high-speed counter or an input edge, and increment a global counter in the interrupt OB.
• PLC tag edge detection. Combine a 1 ms cyclic interrupt OB (OB30–OB38) with an edge flag to derive any frequency by integer division.

11. S7-1200 vs. S7-1500: Clock Memory Behavior

On S7-1500 the same approach applies, with one extra caveat: when the project uses optimized block access for a DB, Merker memory can still be addressed symbolically via the PLC tag table, but any DB declared as optimized will not permit an absolute clock byte inside the DB. Keep the clock byte in the global Merker area.

12. Field-Commissioning Procedure

1. Connect the engineering station to the PLC and go online.
2. Open Online & diagnostics → Diagnostics status; record firmware, serial number, and project checksum.
3. Open the CPU Properties → System and clock memory. Confirm the clock byte address. If none is set, configure one and download.
4. Create a watch table with the eight clock bits, the output coil, and any intermediate tags.
5. Start the CPU in RUN. Verify each bit toggles at the correct period using the Monitor with trigger function.
6. Set up a forced output test on the chosen Q address and measure the pulse train at the terminals with a multimeter in Hz mode or a scope.
7. Document the assigned clock byte, the project checksum, and the verification results in the project handover folder.