Troubleshooting PCS 7 AS-Wide Interconnection Limit Reached Error

1. Problem Description

When configuring AS-Wide Interconnections between two PCS 7 Automation Stations (AS 1 and AS 2) on redundant S7-400H controllers — for example, two CPU 417-5H PN/DP (6ES7417-5HT06-0AB0) stations — the SIMATIC Manager / PCS 7 engineering tool issues the following diagnostic message while editing a CFC chart in OB 3x:

"200 Input interconnections to this partner CPU have already been configured in this OB."

Moving the block to a different OB 3x (e.g., from OB 33 to OB 32) postpones the error, but the second OB will also reject further interconnections after a comparable threshold is reached. The system does not crash, but the engineering tool refuses to compile the new chart until either the number of interconnections is reduced or the transport mechanism is changed.

Symptom summary:

• CFC compile warning or error referring to OB 3x partner CPU interconnections.
• Cross-reference view shows that all "Input" or "Output" chart-in-chart pins on a single partner AS are saturated.
• Behavior is identical in single-station (AS 410) and H-system (AS 410H / AS 417H) topologies; the limit is a CFC / OS communication feature, not a CPU hardware feature.

2. Root Cause Analysis

AS-Wide Interconnections are a PCS 7-specific concept that exchanges process values between the WinCC-based OS archive / faceplate layer and remote AS stations through the plant bus (Industrial Ethernet / PROFINET). The CFC editor manages these links as compiled blocks that map signal sources to signal sinks across AS boundaries.

There are two different throttling models implemented over the lifetime of PCS 7:

The 200-error message displayed in V8.0 SP1 is a legacy diagnostic carried forward from the original V7.1 CFC code path; it is the same string and is triggered when the per-OB partner CPU counter exceeds the legacy limit. The system is, in fact, in the throughput-limited regime, but the CFC UI surfaces the older wording until the chart is moved or reorganized.

3. AS-Wide Interconnection Limits per PCS 7 Version

The exact published figures are version-dependent and must be verified against the locally installed CFC for SIMATIC S7 manual. The table below reflects the values reported in the PCS 7 V8.0 SP4 CFC manual and field references.

4. Throughput-Based Limiting: Bytes/Sec Model

In PCS 7 V7.1 SP1 and later, the hard 200-count limit was replaced with a throughput budget. Each AS-Wide interconnection consumes a number of bytes that is a function of the transported data type and the OB 3x in which the source and sink blocks reside.

Byte weight per interconnection (typical published values):

The per-second contribution of a single interconnection is:

bytes_per_sec = byte_weight / OB_cycle_time_seconds

For example, a single REAL interconnection from a chart in OB 35 (1,000 ms) of AS 1 to a chart in OB 35 of AS 2 contributes 4 bytes / 1 sec = 4 bytes/sec. A BOOL in OB 32 (100 ms) contributes 1 / 0.1 = 10 bytes/sec. The 10,000 bytes/sec ceiling is therefore consumed 25× faster by fast OB connections carrying small types than by slow OB connections.

5. Per-OB 3x Byte Cap (4,800 Bytes)

The CFC V8.0 SP4 manual states that each OB 3x may carry a maximum of 4,800 bytes of AS-Wide interconnection data to a single partner AS. This is a structural cap, not a per-second cap. It exists so that the OB's process image remains schedulable inside its cycle window.

OB 3x cycle time reference values on S7-400 / S7-400H:

Interconnections where the source chart is in OB 33 of AS 1 and the sink chart is in OB 34 of AS 2 are classified as inter-OB and consume more bytes per update than same-OB (e.g., OB 33 to OB 33) connections. The exact multiplier depends on PCS 7 version, but field experience is that inter-OB connections cost approximately 2× to 3× the bytes/sec of same-OB connections because PCS 7 has to bridge two different cyclic task levels.

6. Diagnosing the Limit with Chart Reference Data

Open the project in SIMATIC Manager and navigate to:

1. Select the S7 program of AS 1.
2. Right-click → Chart Reference Data → AS-Wide Interconnections.
3. PCS 7 builds a tabular view that lists every AS-Wide interconnection with: source chart, sink chart, OB 3x of source, OB 3x of sink, byte weight, and computed bytes/sec.

To total the throughput budget for a single partner AS:

total_bytes_per_sec = SUM(bytes_per_sec) for all rows
                    where partner = target_AS

If total_bytes_per_sec is approaching 10,000 bytes/sec, the connection is being throttled. If the per-OB 3x sum is approaching 4,800 bytes, that single OB is at its structural ceiling. The 200-count error appears when the engineering UI's per-OB partner CPU counter (an internal diagnostic) trips its legacy threshold; it is not a real communications failure.

7. Solution Path 1: Re-balance Interconnections Across OB 3x

The first remediation is non-invasive and respects the throughput model.

1. Open Chart Reference Data → AS-Wide Interconnections.
2. Group source and sink charts by OB 3x. Identify all inter-OB pairs (e.g., OB 33 → OB 34).
3. For each pair, calculate the bytes/sec saving if both charts are moved to a single common OB 3x (typically OB 33 or OB 35).
4. Move source/sink charts into the common OB. Use CFC → Block → Move to OB. Re-verify the bytes/sec column.
5. Re-compile the S7 program. The 200-error should not reappear if the per-OB counter drops back below 200.

8. Solution Path 2: Switch to SEND_R / REC_R Blocks

When the throughput cap is structurally unreachable because the application genuinely has more than the supported quantity of interconnections, PCS 7's library blocks SEND_R and REC_R replace AS-Wide interconnections with bulk SEND/RECEIVE telegrams. These are not subject to the 200-count / 4,800-byte/OB 3x limit; they ride on S7 communication connections managed by the CPU's communication resources.

Capacity per SEND_R / REC_R instance (as published in the PCS 7 library):

The classic recipe for replacing 200 single-pin AS-Wide interconnections is to bundle them into seven SEND_R / REC_R pairs (7 × 32 = 224 real values, plus the booleans in a separate pair).

1. Open the CFC library: PCS 7 APL V8.0 SP1 → Communication → SEND_R / REC_R.
2. Drop one SEND_R in the source AS and one REC_R in the destination AS.
3. Connect the 32 real-value inputs of SEND_R to the chart outputs you want to publish; map them 1:1 to the 32 real-value outputs of REC_R on the partner AS.
4. Configure the connection ID. Each SEND_R / REC_R pair consumes one S7 connection; the connection must be defined in NetPro with ISO-on-TCP (TCP native) and a unique Local ID.
5. Compile the program. The Chart Reference Data view will no longer list these exchanges as AS-Wide interconnections; they appear under the SEND/RECEIVE block section instead.

9. CPU Communication Load Settings

Each CPU exposes a Communication share under CPU Properties → Communication. Default values:

• Initial PCS 7 releases: 20 % of the OB 1 priority class reserved for communication.
• Later service packs raised the AS-Wide communication reserve to 30 %.

Procedure to inspect / change the share:

1. In HW Config, open the CPU 417-5H PN/DP properties.
2. Select the Communication tab.
3. Read the Communication reserve / maximum percentage.
4. Increase the value (for example from 20 % to 30 %) only if the application has OB 1 headroom — raising the share steals time from cyclic execution and may extend OB 1 scan time.
5. Download the hardware configuration and verify with a CPU diagnostic buffer readout.

For H-systems, repeat on the standby CPU. H-CPU parameters are kept consistent via the link-up procedure after the next synchronization event.

10. Inter-OB vs Same-OB Optimization Strategy

If a project's AS-Wide interconnection footprint must be reduced by, say, 30 % without dropping signals, the most efficient single change is to collapse inter-OB connections into same-OB connections. A practical approach:

Field result: aligning 60 inter-OB connections into a single common OB typically frees 30 % to 50 % of the throughput budget. The per-OB 3x byte cap is also relaxed because the bytes are no longer spread across two OB contexts.

11. Verification

After any remediation, perform the following checks:

1. Compile clean — Run CFC → Compile → Charts as Program. No warnings about partner CPU interconnections should remain.
2. Reference data recount — Re-open Chart Reference Data → AS-Wide Interconnections. Confirm:
   • No OB 3x exceeds 4,800 bytes for any single partner AS.
   • Aggregate bytes/sec stays below 10,000 (or whatever the current Siemens-published value is for the installed version).
3. Runtime CPU load — In WinCC, open the CPU Diagnostics view. Confirm OB 1 cycle time and communication time are within the budget. For an H-system, confirm both CPUs report the same load after a master/standby switchover test.
4. H-system failover test — Power-down the primary CPU. Verify the standby CPU takes over within the configured H-CPU switchover time and that all AS-Wide interconnections resume without operator-visible gaps in faceplate values.
5. OS archive consistency — Open WinCC Tag Logging and verify that the inter-AS tags are archived continuously across the failover. Any gap larger than the configured archive cycle indicates a buffered-link issue.

12. Troubleshooting Matrix

13. Safety and Performance Considerations

• Never raise the CPU communication reserve above the engineering-tested 30 % for AS-Wide without re-running the application FAT. Closed-loop control blocks that depend on a stable OB 1 budget will misbehave if communication time crowds cyclic time.
• H-system rules: AS-Wide interconnections are evaluated on the primary CPU only. The standby does not double-count the budget, so the per-OB 3x cap is still 4,800 bytes per OB, not per CPU pair.
• Plant-bus segmentation: If AS 1 and AS 2 sit on the same PROFINET ring, the plant-bus load is additive. Use managed switches with IGMP snooping and PROFINET QoS to keep multicast (used by WinCC redundancy) off the AS-Wide link.
• Firmware consistency: V8.0 SP1 must run on firmware that is in the PCS 7 V8.0 SP1 released-by-Siemens list. Mismatched firmware (e.g., a CPU 417-5H with V6.0.7 firmware against a project compiled under V4.5.7) can produce compile-time warnings that look like the 200-interconnection error.

14. Reference: Key Document Anchors

• CFC for SIMATIC S7, V8.0 SP4 manual (Siemens Support entry)
• PCS 7 V8.0 SP1 Compendium, Part A - Configuration Guidelines
• PCS 7 V8.0 SP1 Function Manual - AS-Wide Interconnections
• S7-400H Fault-Tolerant Systems, Manual (CPU 417-5H PN/DP)
• PCS 7 APL Library Reference - SEND_R / REC_R block description